diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-01-01 11:41:52 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-01 11:41:52 +0100 |
| commit | e62d838bd424995d2fcdc9cef1f56752905c3b4d (patch) | |
| tree | 1699bd05ec11dcf7cd38e1141eeeb58019008908 /passes/proc/proc_arst.cc | |
| parent | 327a5d42b6b396f1c210f1579d03a0806a261d84 (diff) | |
Removed SigSpec::extend_xx() api
Diffstat (limited to 'passes/proc/proc_arst.cc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 0874d098..27c6b3bc 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -262,7 +262,7 @@ struct ProcArstPass : public Pass { for (auto &chunk : act.first.chunks()) if (chunk.wire && chunk.wire->attributes.count("\\init")) { RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); - value.extend_xx(chunk.wire->width, false); + value.extend_u0(chunk.wire->width, false); arst_sig.append(chunk); arst_val.append(value.extract(chunk.offset, chunk.width)); } |