Renamed RTLIL::{Module,Cell}::connections to connections_

1 files changed, 15 insertions, 15 deletions

diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 5bb1ab94..2cde749a 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
 		if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
 		{
-			mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
+			mod->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
 		}
 		else
 		{
@@ -96,9 +96,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 			eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
 			eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
-			eq_cell->connections["\\A"] = sig;
-			eq_cell->connections["\\B"] = comp;
-			eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++);
+			eq_cell->connections_["\\A"] = sig;
+			eq_cell->connections_["\\B"] = comp;
+			eq_cell->connections_["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++);
 		}
 	}
 
@@ -122,8 +122,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 		any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
 		any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
-		any_cell->connections["\\A"] = cmp_wire;
-		any_cell->connections["\\Y"] = RTLIL::SigSpec(ctrl_wire);
+		any_cell->connections_["\\A"] = cmp_wire;
+		any_cell->connections_["\\Y"] = RTLIL::SigSpec(ctrl_wire);
 	}
 
 	return RTLIL::SigSpec(ctrl_wire);
@@ -157,10 +157,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 	mux_cell->attributes = sw->attributes;
 
 	mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
-	mux_cell->connections["\\A"] = else_signal;
-	mux_cell->connections["\\B"] = when_signal;
-	mux_cell->connections["\\S"] = ctrl_sig;
-	mux_cell->connections["\\Y"] = RTLIL::SigSpec(result_wire);
+	mux_cell->connections_["\\A"] = else_signal;
+	mux_cell->connections_["\\B"] = when_signal;
+	mux_cell->connections_["\\S"] = ctrl_sig;
+	mux_cell->connections_["\\Y"] = RTLIL::SigSpec(result_wire);
 
 	last_mux_cell = mux_cell;
 	return RTLIL::SigSpec(result_wire);
@@ -169,14 +169,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
 {
 	assert(last_mux_cell != NULL);
-	assert(when_signal.size() == last_mux_cell->connections["\\A"].size());
+	assert(when_signal.size() == last_mux_cell->connections_["\\A"].size());
 
 	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
 	assert(ctrl_sig.size() == 1);
 	last_mux_cell->type = "$pmux";
-	last_mux_cell->connections["\\S"].append(ctrl_sig);
-	last_mux_cell->connections["\\B"].append(when_signal);
-	last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].size();
+	last_mux_cell->connections_["\\S"].append(ctrl_sig);
+	last_mux_cell->connections_["\\B"].append(when_signal);
+	last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections_["\\S"].size();
 }
 
 static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
@@ -256,7 +256,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc)
 		log("  creating decoder for signal `%s'.\n", log_signal(sig));
 
 		RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size()));
-		mod->connections.push_back(RTLIL::SigSig(sig, value));
+		mod->connections_.push_back(RTLIL::SigSig(sig, value));
 	}
 }