diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
| commit | 4c4b6021562c598c4510831bd547edaa97d14dac (patch) | |
| tree | 7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/sat/freduce.cc | |
| parent | f9946232adf887e5aa4a48c64f88eaa17e424009 (diff) | |
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/sat/freduce.cc')
| -rw-r--r-- | passes/sat/freduce.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 5d23318c..f8d5cf6c 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -607,7 +607,7 @@ struct FreduceWorker batches.push_back(sigmap(it.second).to_sigbit_set()); bits_full_total += it.second->width; } - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (ct.cell_known(it.second->type)) { std::set<RTLIL::SigBit> inputs, outputs; for (auto &port : it.second->connections()) { |