diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
| commit | cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch) | |
| tree | 2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/sat/sat.cc | |
| parent | 665759fceee4a0db3e776b7912e976eea2ff29a3 (diff) | |
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/sat/sat.cc')
| -rw-r--r-- | passes/sat/sat.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 4b6b1b71..cc041391 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -321,7 +321,7 @@ struct SatHelper if (design->selected(module, c.second)) { // log("Import cell: %s\n", RTLIL::id2cstr(c.first)); if (satgen.importCell(c.second, timestep)) { - for (auto &p : c.second->connections) + for (auto &p : c.second->connections_) if (ct.cell_output(c.second->type, p.first)) show_drivers.insert(sigmap(p.second), c.second); import_cell_counter++; @@ -505,7 +505,7 @@ struct SatHelper final_signals.add(sig); } else { for (auto &d : drivers) - for (auto &p : d->connections) { + for (auto &p : d->connections_) { if (d->type == "$dff" && p.first == "\\CLK") continue; if (d->type.substr(0, 6) == "$_DFF_" && p.first == "\\C") |