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sat.cc
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Author
Age
*
New upstream version 0.9
Ruben Undheim
2019-10-18
*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
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Added sat -show-regs, -show-public, -show-all
Clifford Wolf
2015-08-18
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Re-created command-reference-manual.tex, copied some doc fixes to online help
Clifford Wolf
2015-08-14
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Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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don't consider blackbox modules in "sat" command
Clifford Wolf
2015-04-18
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Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
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Fixed "sat -initsteps" off-by-one bug
Clifford Wolf
2015-02-22
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Added "sat -stepsize" and "sat -tempinduct-step"
Clifford Wolf
2015-02-21
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sat docu change
Clifford Wolf
2015-02-21
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When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.
Clifford Wolf
2015-02-21
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Added "sat -tempinduct-baseonly -tempinduct-inductonly"
Clifford Wolf
2015-02-21
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Fixed basecase init for "sat -tempinduct"
Clifford Wolf
2015-02-21
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Replaced ezDefaultSAT with ezSatPtr
Clifford Wolf
2015-02-21
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format fixes in "sat -dump_json"
Clifford Wolf
2015-02-19
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Added "sat -dump_json" (WaveJSON format)
Clifford Wolf
2015-02-19
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Improved an error message
Clifford Wolf
2015-01-28
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Added "sat -show-ports"
Clifford Wolf
2015-01-27
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Added log_warning() API
Clifford Wolf
2014-11-09
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Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
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namespace Yosys
Clifford Wolf
2014-09-27
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Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
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azonenberg: Make dump_vcd save model when temporal induction fails due to ste...
Clifford Wolf
2014-08-24
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Added "sat -prove-skip"
Clifford Wolf
2014-08-08
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More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
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Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
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Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
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Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
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Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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now ignore init attributes on non-register wires in sat command
Clifford Wolf
2014-07-05
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Small improvement in SAT log messages
Clifford Wolf
2014-03-13
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Added "sat -dump_cnf"
Clifford Wolf
2014-02-18
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Coding style corrections in SatHelper::dump_model_to_vcd()
Clifford Wolf
2014-02-18
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Added "sat -initsteps"
Clifford Wolf
2014-02-18
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Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups
Clifford Wolf
2014-02-17
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Added "-dump_fail_to_vcd" argument to SAT solver
Andrew Zonenberg
2014-02-17
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Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
Clifford Wolf
2014-02-06
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Added support for sat -show @<sel_name>
Clifford Wolf
2014-02-06
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Added sat -set-init-def and sat -tempinduct-def
Clifford Wolf
2014-02-06
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Added sat -set-init-zero support
Clifford Wolf
2014-02-06
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Added sat -verify and -falsify support for non-prove cases
Clifford Wolf
2014-02-06
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