Added support for shifter cells to SAT generator

2 files changed, 17 insertions, 3 deletions

diff --git a/passes/sat/example.v b/passes/sat/example.v
index 9e8c94b7..aa0ddb6e 100644
--- a/passes/sat/example.v
+++ b/passes/sat/example.v
@@ -51,7 +51,20 @@ endmodule
 
 // ------------------------------------
 
-module example003(clk, rst, y);
+module example003(a_shl, a_shr, a_sshl, a_sshr, sh, y_shl, y_shr, y_sshl, y_sshr);
+
+input [7:0] a_shl, a_shr;
+input signed [7:0] a_sshl, a_sshr;
+input [3:0] sh;
+
+output [7:0] y_shl = a_shl << sh, y_shr = a_shr >> sh;
+output signed [7:0] y_sshl = a_sshl <<< sh, y_sshr = a_sshr >>> sh;
+
+endmodule
+
+// ------------------------------------
+
+module example004(clk, rst, y);
 
 input clk, rst;
 output y;
@@ -59,7 +72,7 @@ output y;
 reg [3:0] counter;
 
 always @(posedge clk)
-	case (1)
+	case (1'b1)
 		rst, counter == 9:
 			counter <= 0;
 		default:
diff --git a/passes/sat/example.ys b/passes/sat/example.ys
index d4037f78..3de8c799 100644
--- a/passes/sat/example.ys
+++ b/passes/sat/example.ys
@@ -2,4 +2,5 @@ read_verilog example.v
 proc; opt_clean
 sat_solve -set y 1'b1 example001
 sat_solve -set y 1'b1 example002
-sat_solve -set y 1'b1 example003
+sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
+sat_solve -set y 1'b1 example004