diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
commit | 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d (patch) | |
tree | 9a847fc2fc608ce9ffbc947bcb18eea2205bb2d5 /passes/sat | |
parent | 7bffde6abdaf6fc2ed090946442f90b2438e6126 (diff) |
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
Diffstat (limited to 'passes/sat')
-rw-r--r-- | passes/sat/eval.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 03a86246..73235e93 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -73,7 +73,7 @@ struct BruteForceEquivChecker sig1.expand(), sig2.expand(); for (size_t i = 0; i < sig1.chunks().size(); i++) if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) - sig2.chunks().at(i) = RTLIL::SigChunk(RTLIL::State::Sx); + sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx); sig1.optimize(), sig2.optimize(); } @@ -299,7 +299,7 @@ struct VlogHammerReporter log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); for (int i = 0; i < sig.size(); i++) if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx) - sig.chunks().at(i).data.bits.at(0) = RTLIL::State::Sx; + sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx; } log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str()); |