Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

2 files changed, 2 insertions, 2 deletions

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 19d32334..ed389f2f 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -296,7 +296,7 @@ namespace
 		SigSet<std::pair<std::string, int>> sig2port;
 
 		// create new cell
-		RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name);
+		RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
 
 		// create cell ports
 		for (auto &it : needle->wires_) {
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 2aa59e61..c2e5960f 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -161,7 +161,7 @@ struct TechmapWorker
 			for (auto &it : tpl->cells_)
 				if (it.first == "\\_TECHMAP_REPLACE_") {
 					orig_cell_name = cell->name;
-					module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
+					module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name);
 					break;
 				}