SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

3 files changed, 3 insertions, 3 deletions

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index a960f2ba..5a729808 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -756,7 +756,7 @@ struct ExtractPass : public Pass {
 					newCell->parameters = cell->parameters;
 					for (auto &conn : cell->connections) {
 						RTLIL::SigSpec sig = sigmap(conn.second);
-						for (auto &chunk : sig.chunks())
+						for (auto &chunk : sig.chunks_rw())
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires.at(chunk.wire->name);
 						newCell->connections[conn.first] = sig;
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index ac41e47c..53c5d104 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo;
 void hilomap_worker(RTLIL::SigSpec &sig)
 {
 	sig.expand();
-	for (auto &c : sig.chunks()) {
+	for (auto &c : sig.chunks_rw()) {
 		if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
 			if (!singleton_mode || last_hi.width == 0) {
 				last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index d3e7e20f..f3b1a0ef 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -47,7 +47,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
 		std::string wire_name = sig.chunks()[i].wire->name;
 		apply_prefix(prefix, wire_name);
 		assert(module->wires.count(wire_name) > 0);
-		sig.chunks()[i].wire = module->wires[wire_name];
+		sig.chunks_rw()[i].wire = module->wires[wire_name];
 	}
 }