Use only module->addCell() and module->remove() to create and delete cells

6 files changed, 59 insertions, 122 deletions

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 4bf73358..c047e418 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -394,28 +394,24 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 	}
 
 	std::map<std::string, int> stats;
-	for (auto cell : cell_list) {
-		cell_mapping &cm = cell_mappings[cell->type];
-		RTLIL::Cell *new_cell = new RTLIL::Cell;
-		new_cell->name = cell->name;
-		new_cell->type = "\\" + cm.cell_name;
+	for (auto cell : cell_list)
+	{
+		auto cell_type = cell->type;
+		auto cell_name = cell->name;
+		auto cell_connections = cell->connections;
+		module->remove(cell);
+
+		cell_mapping &cm = cell_mappings[cell_type];
+		RTLIL::Cell *new_cell = module->addCell(cell_name, "\\" + cm.cell_name);
+
 		for (auto &port : cm.ports) {
 			RTLIL::SigSpec sig;
 			if ('A' <= port.second && port.second <= 'Z') {
-				sig = cell->connections[std::string("\\") + port.second];
+				sig = cell_connections[std::string("\\") + port.second];
 			} else
 			if ('a' <= port.second && port.second <= 'z') {
-				sig = cell->connections[std::string("\\") + char(port.second - ('a' - 'A'))];
-				RTLIL::Cell *inv_cell = new RTLIL::Cell;
-				RTLIL::Wire *inv_wire = new RTLIL::Wire;
-				inv_cell->name = stringf("$dfflibmap$inv$%d", RTLIL::autoidx);
-				inv_wire->name = stringf("$dfflibmap$sig$%d", RTLIL::autoidx++);
-				inv_cell->type = "$_INV_";
-				inv_cell->connections[port.second == 'q' ? "\\Y" : "\\A"] = sig;
-				sig = RTLIL::SigSpec(inv_wire);
-				inv_cell->connections[port.second == 'q' ? "\\A" : "\\Y"] = sig;
-				module->cells[inv_cell->name] = inv_cell;
-				module->wires[inv_wire->name] = inv_wire;
+				sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
+				sig = module->InvGate(NEW_ID, sig);
 			} else
 			if (port.second == '0' || port.second == '1') {
 				sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
@@ -424,9 +420,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 				log_abort();
 			new_cell->connections["\\" + port.first] = sig;
 		}
-		stats[stringf("  mapped %%d %s cells to %s cells.\n", cell->type.c_str(), new_cell->type.c_str())]++;
-		module->cells[cell->name] = new_cell;
-		delete cell;
+
+		stats[stringf("  mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
 	}
 
 	for (auto &stat: stats)
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 4c3aec31..e52c8fe5 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -297,10 +297,7 @@ namespace
 		SigSet<std::pair<std::string, int>> sig2port;
 
 		// create new cell
-		RTLIL::Cell *cell = new RTLIL::Cell;
-		cell->name = stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++);
-		cell->type = needle->name;
-		haystack->add(cell);
+		RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name);
 
 		// create cell ports
 		for (auto &it : needle->wires) {
@@ -333,8 +330,7 @@ namespace
 				}
 			}
 
-			haystack->cells.erase(haystack_cell->name);
-			delete haystack_cell;
+			haystack->remove(haystack_cell);
 		}
 
 		return cell;
@@ -741,9 +737,7 @@ struct ExtractPass : public Pass {
 				}
 
 				for (auto cell : cells) {
-					RTLIL::Cell *newCell = new RTLIL::Cell;
-					newCell->name = cell->name;
-					newCell->type = cell->type;
+					RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
 					newCell->parameters = cell->parameters;
 					for (auto &conn : cell->connections) {
 						std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
@@ -752,7 +746,6 @@ struct ExtractPass : public Pass {
 								chunk.wire = newMod->wires.at(chunk.wire->name);
 						newCell->connections[conn.first] = chunks;
 					}
-					newMod->add(newCell);
 				}
 			}
 
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index 51b8802c..e4153670 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -34,22 +34,16 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 		if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
 			if (!singleton_mode || last_hi == RTLIL::State::Sm) {
 				last_hi = module->addWire(NEW_ID);
-				RTLIL::Cell *cell = new RTLIL::Cell;
-				cell->name = NEW_ID;
-				cell->type = RTLIL::escape_id(hicell_celltype);
+				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
 				cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi;
-				module->add(cell);
 			}
 			bit = last_hi;
 		}
 		if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
 			if (!singleton_mode || last_lo == RTLIL::State::Sm) {
 				last_lo = module->addWire(NEW_ID);
-				RTLIL::Cell *cell = new RTLIL::Cell;
-				cell->name = NEW_ID;
-				cell->type = RTLIL::escape_id(locell_celltype);
+				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
 				cell->connections[RTLIL::escape_id(locell_portname)] = last_lo;
-				module->add(cell);
 			}
 			bit = last_lo;
 		}
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 09147383..7b2484d8 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -176,9 +176,7 @@ struct IopadmapPass : public Pass {
 				{
 					for (int i = 0; i < wire->width; i++)
 					{
-						RTLIL::Cell *cell = new RTLIL::Cell;
-						cell->name = NEW_ID;
-						cell->type = RTLIL::escape_id(celltype);
+						RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
 						cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
 						if (!portname2.empty())
 							cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
@@ -187,14 +185,11 @@ struct IopadmapPass : public Pass {
 						if (!nameparam.empty())
 							cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
 						cell->attributes["\\keep"] = RTLIL::Const(1);
-						module->add(cell);
 					}
 				}
 				else
 				{
-					RTLIL::Cell *cell = new RTLIL::Cell;
-					cell->name = NEW_ID;
-					cell->type = RTLIL::escape_id(celltype);
+					RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
 					cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
 					if (!portname2.empty())
 						cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
@@ -203,7 +198,6 @@ struct IopadmapPass : public Pass {
 					if (!nameparam.empty())
 						cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
 					cell->attributes["\\keep"] = RTLIL::Const(1);
-					module->add(cell);
 				}
 
 				wire->port_id = 0;
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 034677d3..8489e7fd 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -35,12 +35,9 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 	sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
-		RTLIL::Cell *gate = new RTLIL::Cell;
-		gate->name = NEW_ID;
-		gate->type = "$_INV_";
+		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
 		gate->connections["\\A"] = sig_a[i];
 		gate->connections["\\Y"] = sig_y[i];
-		module->add(gate);
 	}
 }
 
@@ -78,12 +75,9 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 		RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y));
 
 		for (int i = 0; i < SIZE(sig_y); i++) {
-			RTLIL::Cell *gate = new RTLIL::Cell;
-			gate->name = NEW_ID;
-			gate->type = "$_INV_";
+			RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
 			gate->connections["\\A"] = sig_t[i];
 			gate->connections["\\Y"] = sig_y[i];
-			module->add(gate);
 		}
 
 		sig_y = sig_t;
@@ -97,13 +91,10 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 	log_assert(!gate_type.empty());
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
-		RTLIL::Cell *gate = new RTLIL::Cell;
-		gate->name = NEW_ID;
-		gate->type = gate_type;
+		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 		gate->connections["\\A"] = sig_a[i];
 		gate->connections["\\B"] = sig_b[i];
 		gate->connections["\\Y"] = sig_y[i];
-		module->add(gate);
 	}
 }
 
@@ -150,14 +141,11 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 				continue;
 			}
 
-			RTLIL::Cell *gate = new RTLIL::Cell;
-			gate->name = NEW_ID;
-			gate->type = gate_type;
+			RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 			gate->connections["\\A"] = sig_a[i];
 			gate->connections["\\B"] = sig_a[i+1];
 			gate->connections["\\Y"] = sig_t[i/2];
 			last_output = &gate->connections["\\Y"];
-			module->add(gate);
 		}
 
 		sig_a = sig_t;
@@ -165,13 +153,10 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	if (cell->type == "$reduce_xnor") {
 		RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
-		RTLIL::Cell *gate = new RTLIL::Cell;
-		gate->name = NEW_ID;
-		gate->type = "$_INV_";
+		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
 		gate->connections["\\A"] = sig_a;
 		gate->connections["\\Y"] = sig_t;
 		last_output = &gate->connections["\\Y"];
-		module->add(gate);
 		sig_a = sig_t;
 	}
 
@@ -195,13 +180,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
 				continue;
 			}
 
-			RTLIL::Cell *gate = new RTLIL::Cell;
-			gate->name = NEW_ID;
-			gate->type = "$_OR_";
+			RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
 			gate->connections["\\A"] = sig[i];
 			gate->connections["\\B"] = sig[i+1];
 			gate->connections["\\Y"] = sig_t[i/2];
-			module->add(gate);
 		}
 
 		sig = sig_t;
@@ -226,12 +208,9 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 		sig_y = sig_y.extract(0, 1);
 	}
 
-	RTLIL::Cell *gate = new RTLIL::Cell;
-	gate->name = NEW_ID;
-	gate->type = "$_INV_";
+	RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
 	gate->connections["\\A"] = sig_a;
 	gate->connections["\\Y"] = sig_y;
-	module->add(gate);
 }
 
 static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
@@ -257,13 +236,10 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == "$logic_or")  gate_type = "$_OR_";
 	log_assert(!gate_type.empty());
 
-	RTLIL::Cell *gate = new RTLIL::Cell;
-	gate->name = NEW_ID;
-	gate->type = gate_type;
+	RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 	gate->connections["\\A"] = sig_a;
 	gate->connections["\\B"] = sig_b;
 	gate->connections["\\Y"] = sig_y;
-	module->add(gate);
 }
 
 static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
@@ -273,14 +249,11 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
-		RTLIL::Cell *gate = new RTLIL::Cell;
-		gate->name = NEW_ID;
-		gate->type = "$_MUX_";
+		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
 		gate->connections["\\A"] = sig_a[i];
 		gate->connections["\\B"] = sig_b[i];
 		gate->connections["\\S"] = cell->connections.at("\\S");
 		gate->connections["\\Y"] = sig_y[i];
-		module->add(gate);
 	}
 }
 
@@ -313,13 +286,10 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
 	std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
 
 	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = new RTLIL::Cell;
-		gate->name = NEW_ID;
-		gate->type = gate_type;
+		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 		gate->connections["\\S"] = sig_s[i];
 		gate->connections["\\R"] = sig_r[i];
 		gate->connections["\\Q"] = sig_q[i];
-		module->add(gate);
 	}
 }
 
@@ -335,13 +305,10 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
 	std::string gate_type = stringf("$_DFF_%c_", clk_pol);
 
 	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = new RTLIL::Cell;
-		gate->name = NEW_ID;
-		gate->type = gate_type;
+		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 		gate->connections["\\C"] = sig_clk;
 		gate->connections["\\D"] = sig_d[i];
 		gate->connections["\\Q"] = sig_q[i];
-		module->add(gate);
 	}
 }
 
@@ -361,15 +328,12 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
 	std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
 
 	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = new RTLIL::Cell;
-		gate->name = NEW_ID;
-		gate->type = gate_type;
+		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 		gate->connections["\\C"] = sig_clk;
 		gate->connections["\\S"] = sig_s[i];
 		gate->connections["\\R"] = sig_r[i];
 		gate->connections["\\D"] = sig_d[i];
 		gate->connections["\\Q"] = sig_q[i];
-		module->add(gate);
 	}
 }
 
@@ -392,14 +356,11 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
 	std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
 
 	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = new RTLIL::Cell;
-		gate->name = NEW_ID;
-		gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0;
+		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
 		gate->connections["\\C"] = sig_clk;
 		gate->connections["\\R"] = sig_rst;
 		gate->connections["\\D"] = sig_d[i];
 		gate->connections["\\Q"] = sig_q[i];
-		module->add(gate);
 	}
 }
 
@@ -415,13 +376,10 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 	std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
 
 	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = new RTLIL::Cell;
-		gate->name = NEW_ID;
-		gate->type = gate_type;
+		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 		gate->connections["\\E"] = sig_en;
 		gate->connections["\\D"] = sig_d[i];
 		gate->connections["\\Q"] = sig_q[i];
-		module->add(gate);
 	}
 }
 
@@ -490,10 +448,8 @@ struct SimplemapPass : public Pass {
 				mappers.at(cell_it.second->type)(mod_it.second, cell_it.second);
 				delete_cells.push_back(cell_it.second);
 			}
-			for (auto &it : delete_cells) {
-				mod_it.second->cells.erase(it->name);
-				delete it;
-			}
+			for (auto c : delete_cells)
+				mod_it.second->remove(c);
 		}
 	}
 } SimplemapPass;
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 8d7b21e0..e8385844 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -114,15 +114,12 @@ struct TechmapWorker
 			log_error("Technology map yielded processes -> this is not supported.\n");
 		}
 
-		// erase from namespace first for _TECHMAP_REPLACE_ to work
-		module->cells.erase(cell->name);
 		std::string orig_cell_name;
-
 		if (!flatten_mode)
 			for (auto &it : tpl->cells)
 				if (it.first == "\\_TECHMAP_REPLACE_") {
 					orig_cell_name = cell->name;
-					cell->name = stringf("$techmap%d", RTLIL::autoidx++) + cell->name;
+					module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
 					break;
 				}
 
@@ -183,20 +180,29 @@ struct TechmapWorker
 			}
 		}
 
-		for (auto &it : tpl->cells) {
-			RTLIL::Cell *c = new RTLIL::Cell(*it.second);
-			if (!flatten_mode && c->type.substr(0, 2) == "\\$")
-				c->type = c->type.substr(1);
-			if (!flatten_mode && c->name == "\\_TECHMAP_REPLACE_")
-				c->name = orig_cell_name;
+		for (auto &it : tpl->cells)
+		{
+			RTLIL::IdString c_name = it.second->name;
+			RTLIL::IdString c_type = it.second->type;
+
+			if (!flatten_mode && c_type.substr(0, 2) == "\\$")
+				c_type = c_type.substr(1);
+
+			if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
+				c_name = orig_cell_name;
 			else
-				apply_prefix(cell->name, c->name);
+				apply_prefix(cell->name, c_name);
+
+			RTLIL::Cell *c = module->addCell(c_name, c_type);
+			c->connections = it.second->connections;
+			c->parameters = it.second->parameters;
+			c->attributes = it.second->attributes;
+			design->select(module, c);
+
 			for (auto &it2 : c->connections) {
 				apply_prefix(cell->name, it2.second, module);
 				port_signal_map.apply(it2.second);
 			}
-			module->add(c);
-			design->select(module, c);
 		}
 
 		for (auto &it : tpl->connections) {
@@ -208,7 +214,7 @@ struct TechmapWorker
 			module->connections.push_back(c);
 		}
 
-		delete cell;
+		module->remove(cell);
 	}
 
 	bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
@@ -254,8 +260,7 @@ struct TechmapWorker
 						if (simplemap_mappers.count(cell->type) == 0)
 							log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
 						simplemap_mappers.at(cell->type)(module, cell);
-						module->cells.erase(cell->name);
-						delete cell;
+						module->remove(cell);
 						cell = NULL;
 						did_something = true;
 						break;