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authorClifford Wolf <clifford@clifford.at>2014-07-27 10:41:42 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 11:32:42 +0200
commit49f72421d5ec499da5da713466e058aae2a67436 (patch)
tree518c98c7f0fe21344f61b04e21b00d8309ae8d0b /passes/techmap
parent675cb93da9e67f5c2fe8a3760de5893176ea906d (diff)
Using new obj iterator API in a few places
Diffstat (limited to 'passes/techmap')
-rw-r--r--passes/techmap/simplemap.cc20
-rw-r--r--passes/techmap/techmap.cc20
2 files changed, 19 insertions, 21 deletions
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 6def1008..b327ba83 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -435,21 +435,19 @@ struct SimplemapPass : public Pass {
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
simplemap_get_mappers(mappers);
- for (auto &mod_it : design->modules_) {
- if (!design->selected(mod_it.second))
+ for (auto mod : design->modules()) {
+ if (!design->selected(mod))
continue;
- std::vector<RTLIL::Cell*> delete_cells;
- for (auto &cell_it : mod_it.second->cells_) {
- if (mappers.count(cell_it.second->type) == 0)
+ std::vector<RTLIL::Cell*> cells = mod->cells();
+ for (auto cell : cells) {
+ if (mappers.count(cell->type) == 0)
continue;
- if (!design->selected(mod_it.second, cell_it.second))
+ if (!design->selected(mod, cell))
continue;
- log("Mapping %s.%s (%s).\n", RTLIL::id2cstr(mod_it.first), RTLIL::id2cstr(cell_it.first), RTLIL::id2cstr(cell_it.second->type));
- mappers.at(cell_it.second->type)(mod_it.second, cell_it.second);
- delete_cells.push_back(cell_it.second);
+ log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
+ mappers.at(cell->type)(mod, cell);
+ mod->remove(cell);
}
- for (auto c : delete_cells)
- mod_it.second->remove(c);
}
}
} SimplemapPass;
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 32e18e08..bcae4409 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -658,9 +658,9 @@ struct FlattenPass : public Pass {
RTLIL::Module *top_mod = NULL;
if (design->full_selection())
- for (auto &mod_it : design->modules_)
- if (mod_it.second->get_bool_attribute("\\top"))
- top_mod = mod_it.second;
+ for (auto mod : design->modules())
+ if (mod->get_bool_attribute("\\top"))
+ top_mod = mod;
bool did_something = true;
std::set<RTLIL::Cell*> handled_cells;
@@ -670,8 +670,8 @@ struct FlattenPass : public Pass {
if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
did_something = true;
} else {
- for (auto &mod_it : design->modules_)
- if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
+ for (auto mod : design->modules())
+ if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, true))
did_something = true;
}
}
@@ -680,12 +680,12 @@ struct FlattenPass : public Pass {
if (top_mod != NULL) {
std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
- for (auto &mod_it : design->modules_)
- if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) {
- new_modules[mod_it.first] = mod_it.second;
+ for (auto mod : design->modules())
+ if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) {
+ new_modules[mod->name] = mod;
} else {
- log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first));
- delete mod_it.second;
+ log("Deleting now unused module %s.\n", log_id(mod));
+ delete mod;
}
design->modules_.swap(new_modules);
}