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authorClifford Wolf <clifford@clifford.at>2014-07-28 11:08:55 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-28 11:27:48 +0200
commit7bd2d1064f2eceddc3c93c121c4154a2f594a040 (patch)
tree563de1df5e323d0f217a51e29acb56c9e9f1327d /passes/techmap
parentd86a25f145012ccb6b2048af3aae22f13b97b505 (diff)
Using log_assert() instead of assert()
Diffstat (limited to 'passes/techmap')
-rw-r--r--passes/techmap/extract.cc3
-rw-r--r--passes/techmap/simplemap.cc1
-rw-r--r--passes/techmap/techmap.cc7
3 files changed, 4 insertions, 7 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 8587f53b..9c5fa7f7 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -23,7 +23,6 @@
#include "libs/subcircuit/subcircuit.h"
#include <algorithm>
#include <stdlib.h>
-#include <assert.h>
#include <stdio.h>
#include <string.h>
@@ -100,7 +99,7 @@ namespace
RTLIL::Cell *haystackCell = (RTLIL::Cell*) haystackUserData;
if (!needleCell || !haystackCell) {
- assert(!needleCell && !haystackCell);
+ log_assert(!needleCell && !haystackCell);
return true;
}
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index b327ba83..5c3e4c68 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -21,7 +21,6 @@
#include "kernel/sigtools.h"
#include "kernel/log.h"
#include <stdlib.h>
-#include <assert.h>
#include <stdio.h>
#include <string.h>
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 79e70a59..5a69baca 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -23,7 +23,6 @@
#include "kernel/toposort.h"
#include "kernel/log.h"
#include <stdlib.h>
-#include <assert.h>
#include <stdio.h>
#include <string.h>
@@ -47,7 +46,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
if (chunk.wire != NULL) {
std::string wire_name = chunk.wire->name;
apply_prefix(prefix, wire_name);
- assert(module->wires_.count(wire_name) > 0);
+ log_assert(module->wires_.count(wire_name) > 0);
chunk.wire = module->wires_[wire_name];
}
sig = chunks;
@@ -167,7 +166,7 @@ struct TechmapWorker
c.second.remove(c.first.size(), c.second.size() - c.first.size());
if (c.second.size() < c.first.size())
c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
- assert(c.first.size() == c.second.size());
+ log_assert(c.first.size() == c.second.size());
if (flatten_mode) {
// more conservative approach:
// connect internal and external wires
@@ -427,7 +426,7 @@ struct TechmapWorker
const char *q = strrchr(p+1, '.');
q = q ? q : p+1;
- assert(!strncmp(q, "_TECHMAP_DO_", 12));
+ log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
while (tpl->wires_.count(new_name))
new_name += "_";