Changed users of cell->connections_ to the new API (sed command)

git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'

6 files changed, 128 insertions, 128 deletions

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index ac0064f7..1dce39f6 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -398,7 +398,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 	{
 		auto cell_type = cell->type;
 		auto cell_name = cell->name;
-		auto cell_connections = cell->connections_;
+		auto cell_connections = cell->connections();
 		module->remove(cell);
 
 		cell_mapping &cm = cell_mappings[cell_type];
@@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 			} else
 			if (port.second != 0)
 				log_abort();
-			new_cell->connections_["\\" + port.first] = sig;
+			new_cell->connections()["\\" + port.first] = sig;
 		}
 
 		stats[stringf("  mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 5dfcd63d..0d8f6ab0 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -125,10 +125,10 @@ namespace
 				RTLIL::Wire *lastHaystackWire = NULL;
 				std::map<RTLIL::IdString, RTLIL::Const> emptyAttr;
 
-				for (auto &conn : needleCell->connections_)
+				for (auto &conn : needleCell->connections())
 				{
 					RTLIL::SigSpec needleSig = conn.second;
-					RTLIL::SigSpec haystackSig = haystackCell->connections_.at(portMapping.at(conn.first));
+					RTLIL::SigSpec haystackSig = haystackCell->connections().at(portMapping.at(conn.first));
 
 					for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
 						RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
@@ -186,7 +186,7 @@ namespace
 			{
 				RTLIL::Cell *cell = cell_it.second;
 				if (!sel || sel->selected(mod, cell))
-					for (auto &conn : cell->connections_) {
+					for (auto &conn : cell->connections()) {
 						RTLIL::SigSpec conn_sig = conn.second;
 						sigmap.apply(conn_sig);
 						for (auto &bit : conn_sig)
@@ -207,7 +207,7 @@ namespace
 				type = type.substr(1);
 			graph.createNode(cell->name, type, (void*)cell);
 
-			for (auto &conn : cell->connections_)
+			for (auto &conn : cell->connections())
 			{
 				graph.createPort(cell->name, conn.first, conn.second.size());
 
@@ -257,7 +257,7 @@ namespace
 		{
 			RTLIL::Cell *cell = cell_it.second;
 			if (sel && !sel->selected(mod, cell))
-				for (auto &conn : cell->connections_)
+				for (auto &conn : cell->connections())
 				{
 					RTLIL::SigSpec conn_sig = conn.second;
 					sigmap.apply(conn_sig);
@@ -305,7 +305,7 @@ namespace
 			if (wire->port_id > 0) {
 				for (int i = 0; i < wire->width; i++)
 					sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
-				cell->connections_[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
+				cell->connections()[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
 			}
 		}
 
@@ -319,13 +319,13 @@ namespace
 			if (needle_cell == NULL)
 				continue;
 
-			for (auto &conn : needle_cell->connections_) {
+			for (auto &conn : needle_cell->connections()) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
 				if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
 					for (int i = 0; i < sig.size(); i++)
 					for (auto &port : sig2port.find(sig[i])) {
-						RTLIL::SigSpec bitsig = haystack_cell->connections_.at(mapping.portMapping[conn.first]).extract(i, 1);
-						cell->connections_.at(port.first).replace(port.second, bitsig);
+						RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1);
+						cell->connections().at(port.first).replace(port.second, bitsig);
 					}
 				}
 			}
@@ -714,7 +714,7 @@ struct ExtractPass : public Pass {
 					cells.insert((RTLIL::Cell*)node.userData);
 
 				for (auto cell : cells)
-				for (auto &conn : cell->connections_) {
+				for (auto &conn : cell->connections()) {
 					RTLIL::SigSpec sig = sigmap(conn.second);
 					for (auto &chunk : sig.chunks())
 						if (chunk.wire != NULL)
@@ -739,12 +739,12 @@ struct ExtractPass : public Pass {
 				for (auto cell : cells) {
 					RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
 					newCell->parameters = cell->parameters;
-					for (auto &conn : cell->connections_) {
+					for (auto &conn : cell->connections()) {
 						std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
 						for (auto &chunk : chunks)
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires.at(chunk.wire->name);
-						newCell->connections_[conn.first] = chunks;
+						newCell->connections()[conn.first] = chunks;
 					}
 				}
 			}
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index 286ad8ac..2e5dd7dc 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_hi == RTLIL::State::Sm) {
 				last_hi = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
-				cell->connections_[RTLIL::escape_id(hicell_portname)] = last_hi;
+				cell->connections()[RTLIL::escape_id(hicell_portname)] = last_hi;
 			}
 			bit = last_hi;
 		}
@@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_lo == RTLIL::State::Sm) {
 				last_lo = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
-				cell->connections_[RTLIL::escape_id(locell_portname)] = last_lo;
+				cell->connections()[RTLIL::escape_id(locell_portname)] = last_lo;
 			}
 			bit = last_lo;
 		}
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index ba9bf51d..199fd602 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -177,9 +177,9 @@ struct IopadmapPass : public Pass {
 					for (int i = 0; i < wire->width; i++)
 					{
 						RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-						cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
+						cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
 						if (!portname2.empty())
-							cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
+							cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
 						if (!widthparam.empty())
 							cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
 						if (!nameparam.empty())
@@ -190,9 +190,9 @@ struct IopadmapPass : public Pass {
 				else
 				{
 					RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-					cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
+					cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
 					if (!portname2.empty())
-						cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
+						cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
 					if (!widthparam.empty())
 						cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
 					if (!nameparam.empty())
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index df7592ce..f8851400 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -29,43 +29,43 @@ extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*,
 
 static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-		gate->connections_["\\A"] = sig_a[i];
-		gate->connections_["\\Y"] = sig_y[i];
+		gate->set("\\A", sig_a[i]);
+		gate->set("\\Y", sig_y[i]);
 	}
 }
 
 static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
-	module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a));
+	module->connect(RTLIL::SigSig(sig_y, sig_a));
 }
 
 static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
-	module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a));
+	module->connect(RTLIL::SigSig(sig_y, sig_a));
 }
 
 static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
-	RTLIL::SigSpec sig_b = cell->connections_.at("\\B");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
+	RTLIL::SigSpec sig_b = cell->get("\\B");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 	sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
@@ -76,8 +76,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 
 		for (int i = 0; i < SIZE(sig_y); i++) {
 			RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-			gate->connections_["\\A"] = sig_t[i];
-			gate->connections_["\\Y"] = sig_y[i];
+			gate->set("\\A", sig_t[i]);
+			gate->set("\\Y", sig_y[i]);
 		}
 
 		sig_y = sig_t;
@@ -92,31 +92,31 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\A"] = sig_a[i];
-		gate->connections_["\\B"] = sig_b[i];
-		gate->connections_["\\Y"] = sig_y[i];
+		gate->set("\\A", sig_a[i]);
+		gate->set("\\B", sig_b[i]);
+		gate->set("\\Y", sig_y[i]);
 	}
 }
 
 static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	if (sig_y.size() == 0)
 		return;
 	
 	if (sig_a.size() == 0) {
-		if (cell->type == "$reduce_and")  module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
-		if (cell->type == "$reduce_or")   module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
-		if (cell->type == "$reduce_xor")  module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
-		if (cell->type == "$reduce_xnor") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
-		if (cell->type == "$reduce_bool") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+		if (cell->type == "$reduce_and")  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+		if (cell->type == "$reduce_or")   module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+		if (cell->type == "$reduce_xor")  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+		if (cell->type == "$reduce_xnor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+		if (cell->type == "$reduce_bool") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 		return;
 	}
 
 	if (sig_y.size() > 1) {
-		module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
+		module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 		sig_y = sig_y.extract(0, 1);
 	}
 
@@ -142,10 +142,10 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-			gate->connections_["\\A"] = sig_a[i];
-			gate->connections_["\\B"] = sig_a[i+1];
-			gate->connections_["\\Y"] = sig_t[i/2];
-			last_output = &gate->connections_["\\Y"];
+			gate->set("\\A", sig_a[i]);
+			gate->set("\\B", sig_a[i+1]);
+			gate->set("\\Y", sig_t[i/2]);
+			last_output = &gate->get("\\Y");
 		}
 
 		sig_a = sig_t;
@@ -154,14 +154,14 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == "$reduce_xnor") {
 		RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-		gate->connections_["\\A"] = sig_a;
-		gate->connections_["\\Y"] = sig_t;
-		last_output = &gate->connections_["\\Y"];
+		gate->set("\\A", sig_a);
+		gate->set("\\Y", sig_t);
+		last_output = &gate->get("\\Y");
 		sig_a = sig_t;
 	}
 
 	if (last_output == NULL) {
-		module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a));
+		module->connect(RTLIL::SigSig(sig_y, sig_a));
 	} else {
 		*last_output = sig_y;
 	}
@@ -181,9 +181,9 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
-			gate->connections_["\\A"] = sig[i];
-			gate->connections_["\\B"] = sig[i+1];
-			gate->connections_["\\Y"] = sig_t[i/2];
+			gate->set("\\A", sig[i]);
+			gate->set("\\B", sig[i+1]);
+			gate->set("\\Y", sig_t[i/2]);
 		}
 
 		sig = sig_t;
@@ -195,39 +195,39 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
 
 static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
 	logic_reduce(module, sig_a);
 
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	if (sig_y.size() == 0)
 		return;
 	
 	if (sig_y.size() > 1) {
-		module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
+		module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 		sig_y = sig_y.extract(0, 1);
 	}
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-	gate->connections_["\\A"] = sig_a;
-	gate->connections_["\\Y"] = sig_y;
+	gate->set("\\A", sig_a);
+	gate->set("\\Y", sig_y);
 }
 
 static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
 	logic_reduce(module, sig_a);
 
-	RTLIL::SigSpec sig_b = cell->connections_.at("\\B");
+	RTLIL::SigSpec sig_b = cell->get("\\B");
 	logic_reduce(module, sig_b);
 
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	if (sig_y.size() == 0)
 		return;
 	
 	if (sig_y.size() > 1) {
-		module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
+		module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 		sig_y = sig_y.extract(0, 1);
 	}
 
@@ -237,40 +237,40 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 	log_assert(!gate_type.empty());
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-	gate->connections_["\\A"] = sig_a;
-	gate->connections_["\\B"] = sig_b;
-	gate->connections_["\\Y"] = sig_y;
+	gate->set("\\A", sig_a);
+	gate->set("\\B", sig_b);
+	gate->set("\\Y", sig_y);
 }
 
 static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
-	RTLIL::SigSpec sig_b = cell->connections_.at("\\B");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
+	RTLIL::SigSpec sig_b = cell->get("\\B");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
-		gate->connections_["\\A"] = sig_a[i];
-		gate->connections_["\\B"] = sig_b[i];
-		gate->connections_["\\S"] = cell->connections_.at("\\S");
-		gate->connections_["\\Y"] = sig_y[i];
+		gate->set("\\A", sig_a[i]);
+		gate->set("\\B", sig_b[i]);
+		gate->set("\\S", cell->get("\\S"));
+		gate->set("\\Y", sig_y[i]);
 	}
 }
 
 static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	int offset = cell->parameters.at("\\OFFSET").as_int();
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
-	module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
+	RTLIL::SigSpec sig_a = cell->get("\\A");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
 }
 
 static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_ab = cell->connections_.at("\\A");
-	sig_ab.append(cell->connections_.at("\\B"));
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
-	module->connections_.push_back(RTLIL::SigSig(sig_y, sig_ab));
+	RTLIL::SigSpec sig_ab = cell->get("\\A");
+	sig_ab.append(cell->get("\\B"));
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	module->connect(RTLIL::SigSig(sig_y, sig_ab));
 }
 
 static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
@@ -279,17 +279,17 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
 	char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 	char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_s = cell->connections_.at("\\SET");
-	RTLIL::SigSpec sig_r = cell->connections_.at("\\CLR");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_s = cell->get("\\SET");
+	RTLIL::SigSpec sig_r = cell->get("\\CLR");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\S"] = sig_s[i];
-		gate->connections_["\\R"] = sig_r[i];
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\S", sig_s[i]);
+		gate->set("\\R", sig_r[i]);
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 
@@ -298,17 +298,17 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
 	int width = cell->parameters.at("\\WIDTH").as_int();
 	char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK");
-	RTLIL::SigSpec sig_d = cell->connections_.at("\\D");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_clk = cell->get("\\CLK");
+	RTLIL::SigSpec sig_d = cell->get("\\D");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type = stringf("$_DFF_%c_", clk_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\C"] = sig_clk;
-		gate->connections_["\\D"] = sig_d[i];
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\C", sig_clk);
+		gate->set("\\D", sig_d[i]);
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 
@@ -319,21 +319,21 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
 	char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 	char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK");
-	RTLIL::SigSpec sig_s = cell->connections_.at("\\SET");
-	RTLIL::SigSpec sig_r = cell->connections_.at("\\CLR");
-	RTLIL::SigSpec sig_d = cell->connections_.at("\\D");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_clk = cell->get("\\CLK");
+	RTLIL::SigSpec sig_s = cell->get("\\SET");
+	RTLIL::SigSpec sig_r = cell->get("\\CLR");
+	RTLIL::SigSpec sig_d = cell->get("\\D");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\C"] = sig_clk;
-		gate->connections_["\\S"] = sig_s[i];
-		gate->connections_["\\R"] = sig_r[i];
-		gate->connections_["\\D"] = sig_d[i];
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\C", sig_clk);
+		gate->set("\\S", sig_s[i]);
+		gate->set("\\R", sig_r[i]);
+		gate->set("\\D", sig_d[i]);
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 
@@ -347,20 +347,20 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
 	while (int(rst_val.size()) < width)
 		rst_val.push_back(RTLIL::State::S0);
 
-	RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK");
-	RTLIL::SigSpec sig_rst = cell->connections_.at("\\ARST");
-	RTLIL::SigSpec sig_d = cell->connections_.at("\\D");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_clk = cell->get("\\CLK");
+	RTLIL::SigSpec sig_rst = cell->get("\\ARST");
+	RTLIL::SigSpec sig_d = cell->get("\\D");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
 	std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
-		gate->connections_["\\C"] = sig_clk;
-		gate->connections_["\\R"] = sig_rst;
-		gate->connections_["\\D"] = sig_d[i];
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\C", sig_clk);
+		gate->set("\\R", sig_rst);
+		gate->set("\\D", sig_d[i]);
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 
@@ -369,17 +369,17 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 	int width = cell->parameters.at("\\WIDTH").as_int();
 	char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_en = cell->connections_.at("\\EN");
-	RTLIL::SigSpec sig_d = cell->connections_.at("\\D");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_en = cell->get("\\EN");
+	RTLIL::SigSpec sig_d = cell->get("\\D");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\E"] = sig_en;
-		gate->connections_["\\D"] = sig_d[i];
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\E", sig_en);
+		gate->set("\\D", sig_d[i]);
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index ab95c003..4c8f9250 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -141,7 +141,7 @@ struct TechmapWorker
 
 		SigMap port_signal_map;
 
-		for (auto &it : cell->connections_) {
+		for (auto &it : cell->connections()) {
 			RTLIL::IdString portname = it.first;
 			if (positional_ports.count(portname) > 0)
 				portname = positional_ports.at(portname);
@@ -169,7 +169,7 @@ struct TechmapWorker
 			if (flatten_mode) {
 				// more conservative approach:
 				// connect internal and external wires
-				module->connections_.push_back(c);
+				module->connect(c);
 			} else {
 				// approach that yields nicer outputs:
 				// replace internal wires that are connected to external wires
@@ -195,19 +195,19 @@ struct TechmapWorker
 			if (!flatten_mode && c->type.substr(0, 2) == "\\$")
 				c->type = c->type.substr(1);
 
-			for (auto &it2 : c->connections_) {
+			for (auto &it2 : c->connections()) {
 				apply_prefix(cell->name, it2.second, module);
 				port_signal_map.apply(it2.second);
 			}
 		}
 
-		for (auto &it : tpl->connections_) {
+		for (auto &it : tpl->connections()) {
 			RTLIL::SigSig c = it;
 			apply_prefix(cell->name, c.first, module);
 			apply_prefix(cell->name, c.second, module);
 			port_signal_map.apply(c.first);
 			port_signal_map.apply(c.second);
-			module->connections_.push_back(c);
+			module->connect(c);
 		}
 
 		module->remove(cell);
@@ -262,7 +262,7 @@ struct TechmapWorker
 						break;
 					}
 
-					for (auto conn : cell->connections_) {
+					for (auto conn : cell->connections()) {
 						if (conn.first.substr(0, 1) == "$")
 							continue;
 						if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
@@ -280,7 +280,7 @@ struct TechmapWorker
 					if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
 						parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
 
-					for (auto conn : cell->connections_) {
+					for (auto conn : cell->connections()) {
 						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
 							std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
 							for (auto &bit : v)
@@ -303,7 +303,7 @@ struct TechmapWorker
 					unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
 					unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
 
-					for (auto conn : cell->connections_)
+					for (auto conn : cell->connections())
 						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
 							for (auto &bit : sigmap(conn.second).to_sigbit_vector())
 								if (unique_bit_id.count(bit) == 0)
@@ -317,7 +317,7 @@ struct TechmapWorker
 					if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
 						parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
 
-					for (auto conn : cell->connections_)
+					for (auto conn : cell->connections())
 						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
 							RTLIL::Const value;
 							for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {