Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

2 files changed, 3 insertions, 3 deletions

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 988917b1..1687a1ff 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -315,7 +315,7 @@ namespace
 			RTLIL::Wire *wire = it.second;
 			if (wire->port_id > 0) {
 				for (int i = 0; i < wire->width; i++)
-					sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair<std::string, int>(wire->name, i));
+					sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
 				cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
 			}
 		}
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 2cb76014..09147383 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -179,9 +179,9 @@ struct IopadmapPass : public Pass {
 						RTLIL::Cell *cell = new RTLIL::Cell;
 						cell->name = NEW_ID;
 						cell->type = RTLIL::escape_id(celltype);
-						cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec::grml(wire, i);
+						cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
 						if (!portname2.empty())
-							cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec::grml(new_wire, i);
+							cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
 						if (!widthparam.empty())
 							cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
 						if (!nameparam.empty())