More RTLIL::Cell API usage cleanups

3 files changed, 4 insertions, 4 deletions

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 000a9ec2..67218600 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -94,7 +94,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
 	bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
 
 	RTLIL::SigSpec sig_a = sigmap(cell->get("\\A"));
-	RTLIL::SigSpec sig_b = sigmap(cell->connections().at(b_name));
+	RTLIL::SigSpec sig_b = sigmap(cell->get(b_name));
 	RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y"));
 
 	if (extend_u0) {
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 198f8347..9ce3b43d 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -629,7 +629,7 @@ struct ExposePass : public Pass {
 
 							RTLIL::SigSpec sig;
 							if (cell->has(p->name))
-								sig = cell->connections().at(p->name);
+								sig = cell->get(p->name);
 							sig.extend(w->width);
 							if (w->port_input)
 								module->connect(RTLIL::SigSig(sig, w));
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 6439302c..b8c349f5 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -128,7 +128,7 @@ namespace
 				for (auto &conn : needleCell->connections())
 				{
 					RTLIL::SigSpec needleSig = conn.second;
-					RTLIL::SigSpec haystackSig = haystackCell->connections().at(portMapping.at(conn.first));
+					RTLIL::SigSpec haystackSig = haystackCell->get(portMapping.at(conn.first));
 
 					for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
 						RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
@@ -324,7 +324,7 @@ namespace
 				if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
 					for (int i = 0; i < sig.size(); i++)
 					for (auto &port : sig2port.find(sig[i])) {
-						RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1);
+						RTLIL::SigSpec bitsig = haystack_cell->get(mapping.portMapping[conn.first]).extract(i, 1);
 						RTLIL::SigSpec new_sig = cell->get(port.first);
 						new_sig.replace(port.second, bitsig);
 						cell->set(port.first, new_sig);