New upstream version 0.7+20180830git0b7a184

5 files changed, 411 insertions, 0 deletions

diff --git a/techlibs/achronix/Makefile.inc b/techlibs/achronix/Makefile.inc
new file mode 100755
index 00000000..994cf001
--- /dev/null
+++ b/techlibs/achronix/Makefile.inc
@@ -0,0 +1,6 @@
+
+OBJS += techlibs/achronix/synth_achronix.o
+
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))
+
diff --git a/techlibs/achronix/speedster22i/cells_arith.v b/techlibs/achronix/speedster22i/cells_arith.v
new file mode 100755
index 00000000..e2194cbd
--- /dev/null
+++ b/techlibs/achronix/speedster22i/cells_arith.v
@@ -0,0 +1,65 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// NOTE: This is still WIP.
+(* techmap_celltype = "$alu" *)
+module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
+   parameter A_SIGNED = 0;
+   parameter B_SIGNED = 0;
+   parameter A_WIDTH  = 1;
+   parameter B_WIDTH  = 1;
+   parameter Y_WIDTH  = 1;
+
+	input [A_WIDTH-1:0] A;
+	input [B_WIDTH-1:0] B;
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	//output [Y_WIDTH-1:0] CO;
+        output                 CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	wire [Y_WIDTH-1:0] AA = A_buf;
+	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+	//wire [Y_WIDTH:0] C = {CO, CI};
+        wire [Y_WIDTH+1:0] COx;
+        wire [Y_WIDTH+1:0] C = {COx, CI};
+
+	/* Start implementation */
+	(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
+	  if(i==Y_WIDTH-1) begin
+	    (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
+            assign CO = COx[Y_WIDTH];
+          end
+	  else
+	    fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
+	  end: slice
+	endgenerate
+	/* End implementation */
+	assign X = AA ^ BB;
+
+endmodule
diff --git a/techlibs/achronix/speedster22i/cells_map.v b/techlibs/achronix/speedster22i/cells_map.v
new file mode 100755
index 00000000..95f5d59c
--- /dev/null
+++ b/techlibs/achronix/speedster22i/cells_map.v
@@ -0,0 +1,72 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Achronix eFPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board/custom chip.
+
+// > Input/Output buffers <
+// Input buffer map
+module \$__inpad (input I, output O);
+    PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
+endmodule
+// Output buffer map
+module \$__outpad (input I, output O);
+    PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
+endmodule
+// > end buffers <
+
+// > Look-Up table <
+// > VT: I still think Achronix folks would have choosen a better \
+// >     logic architecture.
+// LUT Map
+module \$lut (A, Y);
+   parameter WIDTH  = 0;
+   parameter LUT    = 0;
+   input [WIDTH-1:0] A;
+   output 	     Y;
+   generate
+      if (WIDTH == 1) begin
+	   // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
+         LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+           (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
+      end else
+      if (WIDTH == 2) begin
+              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
+      end else
+      if(WIDTH == 3) begin
+	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ 
+                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
+      end else
+      if(WIDTH == 4) begin
+             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ 
+               (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
+      end else
+	   wire _TECHMAP_FAIL_ = 1;
+   endgenerate
+endmodule 
+// > end LUT <
+
+// > Flops <
+// DFF flop
+module  \$_DFF_P_ (input D, C, output Q);
+   DFF _TECHMAP_REPLACE_ 
+     (.q(Q), .d(D), .ck(C));
+endmodule 
+
diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
new file mode 100755
index 00000000..da23fed7
--- /dev/null
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -0,0 +1,80 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Achronix eFPGA technology sim models. User must first simulate the generated \
+// > netlist before going to test it on board/custom chip.
+// > Changelog: 1) Removed unused VCC/GND modules
+// >            2) Altera comments here (?). Removed.
+// >            3) Reusing LUT sim model, removed wrong wires and parameters.
+
+module PADIN (output padout, input padin);
+   assign padout = padin;
+endmodule
+
+module PADOUT (output padout, input padin, input oe);
+   assign padout  = padin;
+   assign oe = oe;
+endmodule 
+
+module LUT4 (output dout,
+             input  din0, din1, din2, din3);
+
+parameter [15:0] lut_function = 16'hFFFF;
+reg combout_rt;
+wire dataa_w;
+wire datab_w;
+wire datac_w;
+wire datad_w;
+
+assign dataa_w = din0;
+assign datab_w = din1;
+assign datac_w = din2;
+assign datad_w = din3;
+
+function lut_data;
+input [15:0] mask;
+input        dataa, datab, datac, datad;
+reg [7:0]   s3;
+reg [3:0]   s2;
+reg [1:0]   s1;
+  begin
+       s3 = datad ? mask[15:8] : mask[7:0];
+       s2 = datac ?   s3[7:4]  :   s3[3:0];
+       s1 = datab ?   s2[3:2]  :   s2[1:0];
+       lut_data = dataa ? s1[1] : s1[0];
+  end
+endfunction
+
+always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
+   combout_rt = lut_data(lut_function, dataa_w, datab_w,
+                         datac_w, datad_w);
+end
+assign dout = combout_rt & 1'b1;
+endmodule 
+
+module DFF (output q,
+            input  d, ck);
+   reg             q;
+   always @(posedge ck)
+     q <= d;
+   
+endmodule
+
+
+
diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
new file mode 100755
index 00000000..92b10781
--- /dev/null
+++ b/techlibs/achronix/synth_achronix.cc
@@ -0,0 +1,188 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthAchronixPass : public ScriptPass {
+  SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
+
+  void help() YS_OVERRIDE
+  {
+    //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+    log("\n");
+    log("    synth_achronix [options]\n");
+    log("\n");
+    log("This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.\n");
+    log("\n");
+    log("    -top <module>\n");
+    log("        use the specified module as top module (default='top')\n");
+    log("\n");
+    log("    -vout <file>\n");
+    log("        write the design to the specified Verilog netlist file. writing of an\n");
+    log("        output file is omitted if this parameter is not specified.\n");
+    log("\n");
+    log("    -run <from_label>:<to_label>\n");
+    log("        only run the commands between the labels (see below). an empty\n");
+    log("        from label is synonymous to 'begin', and empty to label is\n");
+    log("        synonymous to the end of the command list.\n");
+    log("\n");
+    log("    -noflatten\n");
+    log("        do not flatten design before synthesis\n");
+    log("\n");
+    log("    -retime\n");
+    log("        run 'abc' with -dff option\n");
+    log("\n");
+    log("\n");
+    log("The following commands are executed by this synthesis command:\n");
+    help_script();
+    log("\n");
+  }
+
+  string top_opt, family_opt, vout_file;
+  bool retime, flatten;
+
+  void clear_flags() YS_OVERRIDE
+  {
+    top_opt = "-auto-top";
+    vout_file = "";
+    retime = false;
+    flatten = true;
+  }
+
+  void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+  {
+    string run_from, run_to;
+    clear_flags();
+
+    size_t argidx;
+    for (argidx = 1; argidx < args.size(); argidx++)
+      {
+        if (args[argidx] == "-top" && argidx+1 < args.size()) {
+          top_opt = "-top " + args[++argidx];
+          continue;
+        }
+        if (args[argidx] == "-vout" && argidx+1 < args.size()) {
+          vout_file = args[++argidx];
+          continue;
+        }
+        if (args[argidx] == "-run" && argidx+1 < args.size()) {
+          size_t pos = args[argidx+1].find(':');
+          if (pos == std::string::npos)
+            break;
+          run_from = args[++argidx].substr(0, pos);
+          run_to = args[argidx].substr(pos+1);
+          continue;
+        }
+        if (args[argidx] == "-flatten") {
+          flatten = true;
+          continue;
+        }
+        if (args[argidx] == "-retime") {
+          retime = true;
+          continue;
+        }
+        break;
+      }
+    extra_args(args, argidx, design);
+
+    if (!design->full_selection())
+      log_cmd_error("This comannd only operates on fully selected designs!\n");
+
+    log_header(design, "Executing SYNTH_ACHRONIX pass.\n");
+    log_push();
+
+    run_script(design, run_from, run_to);
+
+    log_pop();
+  }
+
+  void script() YS_OVERRIDE
+  {
+    if (check_label("begin"))
+      {
+        run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
+        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+      }
+
+    if (flatten && check_label("flatten", "(unless -noflatten)"))
+      {
+        run("proc");
+        run("flatten");
+        run("tribuf -logic");
+        run("deminout");
+      }
+
+    if (check_label("coarse"))
+      {
+        run("synth -run coarse");
+      }
+
+    if (check_label("fine"))
+      {
+        run("opt -fast -mux_undef -undriven -fine -full");
+        run("memory_map");
+        run("opt -undriven -fine");
+        run("dffsr2dff");
+        run("dff2dffe -direct-match $_DFF_*");
+        run("opt -fine");
+        run("techmap -map +/techmap.v");
+        run("opt -full");
+        run("clean -purge");
+        run("setundef -undriven -zero");
+        if (retime || help_mode)
+          run("abc -markgroups -dff", "(only if -retime)");
+      }
+
+    if (check_label("map_luts"))
+      {
+        run("abc -lut 4" + string(retime ? " -dff" : ""));
+        run("clean");
+      }
+
+    if (check_label("map_cells"))
+      {
+        run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
+        run("techmap -map +/achronix/speedster22i/cells_map.v");
+        // VT: not done yet run("dffinit -highlow -ff DFF q power_up");
+        run("clean -purge");
+      }
+
+    if (check_label("check"))
+      {
+        run("hierarchy -check");
+        run("stat");
+        run("check -noinit");
+      }
+
+    if (check_label("vout"))
+      {
+        if (!vout_file.empty() || help_mode)
+          run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix syn_ %s",
+                      help_mode ? "<file-name>" : vout_file.c_str()));
+      }
+  }
+} SynthAchronixPass;
+
+PRIVATE_NAMESPACE_END