Import yosys_0.7.orig.tar.gz

[dgit import orig yosys_0.7.orig.tar.gz]

1 files changed, 27 insertions, 0 deletions

diff --git a/techlibs/common/adff2dff.v b/techlibs/common/adff2dff.v
new file mode 100644
index 00000000..86744d41
--- /dev/null
+++ b/techlibs/common/adff2dff.v
@@ -0,0 +1,27 @@
+(* techmap_celltype = "$adff" *)
+module adff2dff (CLK, ARST, D, Q);
+	parameter WIDTH = 1;
+	parameter CLK_POLARITY = 1;
+	parameter ARST_POLARITY = 1;
+	parameter ARST_VALUE = 0;
+
+	input CLK, ARST;
+	input [WIDTH-1:0] D;
+	output reg [WIDTH-1:0] Q;
+	wire reg [WIDTH-1:0] NEXT_Q;
+
+	wire [1023:0] _TECHMAP_DO_ = "proc;;";
+
+	always @*
+		if (ARST == ARST_POLARITY)
+			NEXT_Q <= ARST_VALUE;
+		else
+			NEXT_Q <= D;
+
+	if (CLK_POLARITY)
+		always @(posedge CLK)
+			Q <= NEXT_Q;
+	else
+		always @(negedge CLK)
+			Q <= NEXT_Q;
+endmodule