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author | Clifford Wolf <clifford@clifford.at> | 2014-08-07 16:14:38 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-08-07 16:14:38 +0200 |
commit | 312ee00c9e279a91f336acef26dd064c25f42ed5 (patch) | |
tree | e9fc1d70b7677ef6961f03fa3fff0f846bdc8aaf /techlibs/common/adff2dff.v | |
parent | d259abbda2b9d568228dc8d0bed2d0b0d88d7b4f (diff) |
Added adff2dff.v (for techmap -share_map)
Diffstat (limited to 'techlibs/common/adff2dff.v')
-rw-r--r-- | techlibs/common/adff2dff.v | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/techlibs/common/adff2dff.v b/techlibs/common/adff2dff.v new file mode 100644 index 00000000..86744d41 --- /dev/null +++ b/techlibs/common/adff2dff.v @@ -0,0 +1,27 @@ +(* techmap_celltype = "$adff" *) +module adff2dff (CLK, ARST, D, Q); + parameter WIDTH = 1; + parameter CLK_POLARITY = 1; + parameter ARST_POLARITY = 1; + parameter ARST_VALUE = 0; + + input CLK, ARST; + input [WIDTH-1:0] D; + output reg [WIDTH-1:0] Q; + wire reg [WIDTH-1:0] NEXT_Q; + + wire [1023:0] _TECHMAP_DO_ = "proc;;"; + + always @* + if (ARST == ARST_POLARITY) + NEXT_Q <= ARST_VALUE; + else + NEXT_Q <= D; + + if (CLK_POLARITY) + always @(posedge CLK) + Q <= NEXT_Q; + else + always @(negedge CLK) + Q <= NEXT_Q; +endmodule |