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author | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
commit | 369bf81a7049c96f62af084bb5007fbf45e36ab4 (patch) | |
tree | 92071580c9bd60888ee5861d59457947a8adfde7 /techlibs/common/simlib.v | |
parent | ecc30255ba70910777a4586f5bd6abc818073293 (diff) |
Added support for non-const === and !== (for miter circuits)
Diffstat (limited to 'techlibs/common/simlib.v')
-rw-r--r-- | techlibs/common/simlib.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index b4440ea8..034244ca 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -376,6 +376,42 @@ endmodule // -------------------------------------------------------- +module \$eqx (A, B, Y); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; + +`INPUT_A +`INPUT_B +output [Y_WIDTH-1:0] Y; + +assign Y = A_BUF.val === B_BUF.val; + +endmodule + +// -------------------------------------------------------- + +module \$nex (A, B, Y); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; + +`INPUT_A +`INPUT_B +output [Y_WIDTH-1:0] Y; + +assign Y = A_BUF.val !== B_BUF.val; + +endmodule + +// -------------------------------------------------------- + module \$ge (A, B, Y); parameter A_SIGNED = 0; |