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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:20 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:20 +0200 |
| commit | 5033b51947a6ef02cb785b5622e993335efa750a (patch) | |
| tree | 7bed18c526bd94917fa2f08e3df12209863698a1 /techlibs/intel/common/brams.txt | |
| parent | fefe0fc0430f4f173a25e674708aa0f4f0854b31 (diff) | |
New upstream version 0.7+20180830git0b7a184
Diffstat (limited to 'techlibs/intel/common/brams.txt')
| -rw-r--r-- | techlibs/intel/common/brams.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams.txt new file mode 100644 index 00000000..3bf21afc --- /dev/null +++ b/techlibs/intel/common/brams.txt @@ -0,0 +1,33 @@ +bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL + init 1 + abits 13 @M1 + dbits 1 @M1 + abits 12 @M2 + dbits 2 @M2 + abits 11 @M3 + dbits 4 @M3 + abits 10 @M4 + dbits 8 @M4 + abits 10 @M5 + dbits 9 @M5 + abits 9 @M6 + dbits 16 @M6 + abits 9 @M7 + dbits 18 @M7 + abits 8 @M8 + dbits 32 @M8 + abits 8 @M9 + dbits 36 @M9 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL + min efficiency 2 + make_transp +endmatch |