Imported GIT HEAD: 0.8+20190328git32bd0f2

5 files changed, 18 insertions, 18 deletions

diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map.v
index fae4af2a..d0f07c1d 100644
--- a/techlibs/intel/common/brams_map.v
+++ b/techlibs/intel/common/brams_map.v
@@ -2,8 +2,8 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
 
    parameter CFG_ABITS = 8;
    parameter CFG_DBITS = 36;
-   parameter ABITS = "1";
-   parameter DBITS = "1";
+   parameter ABITS = 1;
+   parameter DBITS = 1;
    parameter CLKPOL2 = 1;
    parameter CLKPOL3 = 1;
 
@@ -63,21 +63,21 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
                  .width_byteena_a                (1), // Forced value
                  .numwords_b                     ( NUMWORDS     ),
                  .numwords_a                     ( NUMWORDS     ),
-                 .widthad_b                      ( CFG_ABITS    ),
-                 .width_b                        ( CFG_DBITS    ),
-                 .widthad_a                      ( CFG_ABITS    ),
-                 .width_a                        ( CFG_DBITS    )
+                 .widthad_b                      ( CFG_DBITS    ),
+                 .width_b                        ( CFG_ABITS    ),
+                 .widthad_a                      ( CFG_DBITS    ),
+                 .width_a                        ( CFG_ABITS    )
                  ) _TECHMAP_REPLACE_ (
                                       .data_a(B1DATA),
                                       .address_a(B1ADDR),
                                       .wren_a(B1EN),
                                       .rden_a(A1EN),
                                       .q_a(A1DATA),
-                                      .data_b(1'b0),
+                                      .data_b(B1DATA),
                                       .address_b(0),
                                       .wren_b(1'b0),
                                       .rden_b(1'b0),
-                                      .q_b(1'b0),
+                                      .q_b(),
                                       .clock0(CLK2),
                                       .clock1(1'b1), // Unused in single port mode
                                       .clocken0(1'b1),
diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v
index b3a11272..49e36aa2 100644
--- a/techlibs/intel/cycloneive/arith_map.v
+++ b/techlibs/intel/cycloneive/arith_map.v
@@ -32,7 +32,7 @@ module fa
    wire   VCC;
 
    assign VCC = 1'b1;
-   
+
    cycloneiv_lcell_comb gen_sum_0 (.combout(sum_x),
                                    .dataa(a_c),
                                    .datab(b_c),
@@ -40,7 +40,7 @@ module fa
                                    .datad(VCC));
    defparam syn__05_.lut_mask = 16'b1001011010010110;
    defparam syn__05_.sum_lutc_input = "datac";
-   
+
    cycloneiv_lcell_comb gen_cout_0 (.combout(cout_t),
                                     .dataa(cin_c),
                                     .datab(b_c),
@@ -48,11 +48,11 @@ module fa
                                     .datad(VCC));
    defparam syn__06_.lut_mask = 16'b1110000011100000;
    defparam syn__06_.sum_lutc_input = "datac";
-   
+
 endmodule // fa
 
 module f_stage();
-   
+
 endmodule // f_stage
 
 module f_end();
@@ -88,7 +88,7 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
           .cin_c(C[0]),
           .cout_t(C0[1]),
           .sum_x(Y[0]));
-   
+
    genvar i;
    generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
       cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v
index bd60d4e1..f8d142bc 100644
--- a/techlibs/intel/cyclonev/cells_map.v
+++ b/techlibs/intel/cyclonev/cells_map.v
@@ -76,7 +76,7 @@ module \$lut (A, Y);
    wire              VCC;
    wire              GND;
    assign {VCC,GND} = {1'b1,1'b0};
-   
+
    generate
       if (WIDTH == 1) begin
 	 assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
@@ -151,7 +151,7 @@ module \$lut (A, Y);
                     TODO: There's not a just 7-input function on Cyclone V, see the following note:
                     **Extended LUT Mode**
                     Use extended LUT mode to implement a specific set of 7-input functions. The set must
-                    be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs. 
+                    be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
                     [source](Device Interfaces and Integration Basics for Cyclone V Devices).
                   end*/
                   else
diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v
index 5ecdabcf..fa27c2c8 100644
--- a/techlibs/intel/cyclonev/cells_sim.v
+++ b/techlibs/intel/cyclonev/cells_sim.v
@@ -54,7 +54,7 @@ module cyclonev_lcell_comb
    // Internal variables
    // Sub mask for fragmented LUTs
    wire [15:0] mask_a, mask_b, mask_c, mask_d;
-   // Independant output for fragmented LUTs
+   // Independent output for fragmented LUTs
    wire        output_0, output_1, output_2, output_3;
    // Extended mode uses mux to define the output
    wire        mux_0, mux_1;
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index d74f295e..0f1d7a7b 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -131,8 +131,8 @@ struct SynthIntelPass : public ScriptPass {
           nobram = true;
           continue;
         }
-        if (args[argidx] == "-flatten") {
-          flatten = true;
+        if (args[argidx] == "-noflatten") {
+          flatten = false;
           continue;
         }
         if (args[argidx] == "-retime") {