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authorClifford Wolf <clifford@clifford.at>2015-01-05 13:59:04 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-05 13:59:04 +0100
commit9ea2511fe87a9a3a4dd179101f42982ed62e78c0 (patch)
treef9c1e518276935d7243bd4e460ea06c182d5e64c /techlibs/xilinx/brams.v
parent8898897f7b397a09c94e4850ef6146ee5b09677b (diff)
Towards Xilinx bram support
Diffstat (limited to 'techlibs/xilinx/brams.v')
-rw-r--r--techlibs/xilinx/brams.v5
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v
index 067ca8b2..aaab8d47 100644
--- a/techlibs/xilinx/brams.v
+++ b/techlibs/xilinx/brams.v
@@ -29,6 +29,7 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
.RAM_MODE("SDP"),
.READ_WIDTH_A(72),
.WRITE_WIDTH_B(72),
+ .WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
) _TECHMAP_REPLACE_ (
.DOBDO(DO[63:32]),
@@ -41,7 +42,7 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
.DIPADIP(DIP[3:0]),
.ADDRARDADDR(A1ADDR_16),
- .CLKARDCLK(CLK2 == |CLKPOL2),
+ .CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
.ENARDEN(|1),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
@@ -49,7 +50,7 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
.WEA(4'b0),
.ADDRBWRADDR(B1ADDR_16),
- .CLKBWRCLK(CLK3 == |CLKPOL3),
+ .CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),