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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-27 13:12:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-27 13:12:26 +0200 |
| commit | 6685ad436e971ff896b260a782fad1edd3accc89 (patch) | |
| tree | 3dae61a958be2dd46a1fe898a482acf359070002 /techlibs | |
| parent | 5059b3166098044a87b3d0b7f3ae2957df7e6194 (diff) | |
Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx7/run_testbench.sh | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/techlibs/xilinx7/run_testbench.sh b/techlibs/xilinx7/run_testbench.sh index 970fef46..31da59eb 100644 --- a/techlibs/xilinx7/run_testbench.sh +++ b/techlibs/xilinx7/run_testbench.sh @@ -2,7 +2,7 @@ set -ex -XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/ +XILINX_DIR=/opt/Xilinx/14.2/ISE_DS/ISE/ ../../yosys - <<- EOT # read design @@ -20,6 +20,7 @@ XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/ # write netlist write_verilog -noattr testbench_synth.v + write_edif testbench_synth.edif EOT iverilog -o testbench_gold counter_tb.v counter.v @@ -35,7 +36,14 @@ else exit 1 fi +if [ "$*" = "-map" ]; then + set -x + $XILINX_DIR/bin/lin64/edif2ngd testbench_synth.edif + $XILINX_DIR/bin/lin64/ngdbuild -p xc7k70t testbench_synth +fi + if [ "$*" = "-clean" ]; then - rm -f testbench_{synth.v,{gold,gate}{,.txt}} + rm -rf netlist.lst _xmsgs/ + rm -f testbench_{synth,gold,gate}* fi |