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authorRuben Undheim <ruben.undheim@gmail.com>2019-10-18 19:56:51 +0000
committerRuben Undheim <ruben.undheim@gmail.com>2019-10-18 19:56:51 +0000
commit1f6bb85359149a016811e7e7fef980c3d45211e7 (patch)
tree749672f9a104cbfb25bb02acad6cb731724b9d56 /tests/memories/issue00335.v
parentff5734b20220e6fb4a3913cf5279ed94bb5156ea (diff)
New upstream version 0.9
Diffstat (limited to 'tests/memories/issue00335.v')
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diff --git a/tests/memories/issue00335.v b/tests/memories/issue00335.v
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+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module ram2 (input clk,
+ input sel,
+ input we,
+ input [SIZE-1:0] adr,
+ input [63:0] dat_i,
+ output reg [63:0] dat_o);
+ parameter SIZE = 5; // Address size
+
+ reg [63:0] mem [0:(1 << SIZE)-1];
+ integer i;
+
+ initial begin
+ for (i = 0; i < (1<<SIZE) - 1; i = i + 1)
+ mem[i] <= 0;
+ end
+
+ always @(posedge clk)
+ if (sel) begin
+ if (~we)
+ dat_o <= mem[adr];
+ else
+ mem[adr] <= dat_i;
+ end
+endmodule