Added test cases from 2012 paper on comparison of foss verilog synthesis tools

1 files changed, 10 insertions, 0 deletions

diff --git a/tests/simple/always01.v b/tests/simple/always01.v
new file mode 100644
index 00000000..21379cb0
--- /dev/null
+++ b/tests/simple/always01.v
@@ -0,0 +1,10 @@
+module uut_always01(clock, reset, count);
+
+input clock, reset;
+output [3:0] count;
+reg [3:0] count;
+
+always @(posedge clock)
+	count <= reset ?  0 : count + 1;
+
+endmodule