Added test cases from 2012 paper on comparison of foss verilog synthesis tools

1 files changed, 16 insertions, 0 deletions

diff --git a/tests/simple/arrays01.v b/tests/simple/arrays01.v
new file mode 100644
index 00000000..bd0eda29
--- /dev/null
+++ b/tests/simple/arrays01.v
@@ -0,0 +1,16 @@
+module uut_arrays01(clock, we, addr, wr_data, rd_data);
+
+input clock, we;
+input [3:0] addr, wr_data;
+output [3:0] rd_data;
+reg [3:0] rd_data;
+
+reg [3:0] memory [15:0];
+
+always @(posedge clock) begin
+	if (we)
+		memory[addr] <= wr_data;
+	rd_data <= memory[addr];
+end
+
+endmodule