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author | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:17:56 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:17:56 +0200 |
commit | 5640b7d6078a681e33e85f06920394204f41c875 (patch) | |
tree | 96ebae5ed0626ae5238fe8b794e50e0cb9d87e7c /tests/simple/forgen02.v | |
parent | 04843bdcbeb62a202a6372ea5464de8c7ea66820 (diff) |
Added test cases from 2012 paper on comparison of foss verilog synthesis tools
Diffstat (limited to 'tests/simple/forgen02.v')
-rw-r--r-- | tests/simple/forgen02.v | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/tests/simple/forgen02.v b/tests/simple/forgen02.v new file mode 100644 index 00000000..14af070c --- /dev/null +++ b/tests/simple/forgen02.v @@ -0,0 +1,30 @@ +module uut_forgen02(a, b, cin, y, cout); + +parameter WIDTH = 8; + +input [WIDTH-1:0] a, b; +input cin; + +output [WIDTH-1:0] y; +output cout; + +genvar i; +wire [WIDTH-1:0] carry; + +generate + for (i = 0; i < WIDTH; i=i+1) begin:adder + wire [2:0] D; + assign D[1:0] = { a[i], b[i] }; + if (i == 0) begin:chain + assign D[2] = cin; + end else begin:chain + assign D[2] = carry[i-1]; + end + assign y[i] = ^D; + assign carry[i] = &D[1:0] | (^D[1:0] & D[2]); + end +endgenerate + +assign cout = carry[WIDTH-1]; + +endmodule |