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author | Clifford Wolf <clifford@clifford.at> | 2014-06-07 12:18:00 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-06-07 12:26:11 +0200 |
commit | 3af7c69d1e3c17d7aaa5d3a7da9f8a2ae12ed9bf (patch) | |
tree | 756e8985a79d7f4d1f93cca435882f5b45eada19 /tests/simple/repwhile.v | |
parent | 744e51846776a304828301914f5cd74fb7d0a5ca (diff) |
added tests for new verilog features
Diffstat (limited to 'tests/simple/repwhile.v')
-rw-r--r-- | tests/simple/repwhile.v | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/tests/simple/repwhile.v b/tests/simple/repwhile.v index 8c5b4b37..cde37c56 100644 --- a/tests/simple/repwhile.v +++ b/tests/simple/repwhile.v @@ -1,4 +1,5 @@ -module test001(output [63:0] y); +module test001(input [5:0] a, output [7:0] y, output [31:0] x); + function [7:0] mylog2; input [31:0] value; begin @@ -10,11 +11,26 @@ module test001(output [63:0] y); end endfunction - genvar i; - generate + function [31:0] myexp2; + input [7:0] value; + begin + myexp2 = 1; + repeat (value) + myexp2 = myexp2 << 1; + end + endfunction + + reg [7:0] y_table [63:0]; + reg [31:0] x_table [63:0]; + + integer i; + initial begin for (i = 0; i < 64; i = i+1) begin - localparam tmp = mylog2(i); - assign y[i] = tmp; + y_table[i] <= mylog2(i); + x_table[i] <= myexp2(i); end - endgenerate + end + + assign y = y_table[a]; + assign x = x_table[a]; endmodule |