Added xsthammer report generator

1 files changed, 24 insertions, 12 deletions

diff --git a/tests/xsthammer/xl_cells.v b/tests/xsthammer/xl_cells.v
index d2badcff..638053fe 100644
--- a/tests/xsthammer/xl_cells.v
+++ b/tests/xsthammer/xl_cells.v
@@ -12,12 +12,14 @@ assign O = I;
 endmodule
 
 module GND(G);
-output G = 0;
+output G;
+assign G = 0;
 endmodule
 
 module INV(O, I);
 input I;
-output O = !I;
+output O;
+assign O = !I;
 endmodule
 
 module LUT1(O, I0);
@@ -25,7 +27,8 @@ parameter INIT = 0;
 input I0;
 wire [1:0] lutdata = INIT;
 wire [0:0] idx = { I0 };
-output O = lutdata[idx];
+output O;
+assign O = lutdata[idx];
 endmodule
 
 module LUT2(O, I0, I1);
@@ -33,7 +36,8 @@ parameter INIT = 0;
 input I0, I1;
 wire [3:0] lutdata = INIT;
 wire [1:0] idx = { I1, I0 };
-output O = lutdata[idx];
+output O;
+assign O = lutdata[idx];
 endmodule
 
 module LUT3(O, I0, I1, I2);
@@ -41,7 +45,8 @@ parameter INIT = 0;
 input I0, I1, I2;
 wire [7:0] lutdata = INIT;
 wire [2:0] idx = { I2, I1, I0 };
-output O = lutdata[idx];
+output O;
+assign O = lutdata[idx];
 endmodule
 
 module LUT4(O, I0, I1, I2, I3);
@@ -49,7 +54,8 @@ parameter INIT = 0;
 input I0, I1, I2, I3;
 wire [15:0] lutdata = INIT;
 wire [3:0] idx = { I3, I2, I1, I0 };
-output O = lutdata[idx];
+output O;
+assign O = lutdata[idx];
 endmodule
 
 module LUT5(O, I0, I1, I2, I3, I4);
@@ -57,7 +63,8 @@ parameter INIT = 0;
 input I0, I1, I2, I3, I4;
 wire [31:0] lutdata = INIT;
 wire [4:0] idx = { I4, I3, I2, I1, I0 };
-output O = lutdata[idx];
+output O;
+assign O = lutdata[idx];
 endmodule
 
 module LUT6(O, I0, I1, I2, I3, I4, I5);
@@ -65,25 +72,30 @@ parameter INIT = 0;
 input I0, I1, I2, I3, I4, I5;
 wire [63:0] lutdata = INIT;
 wire [5:0] idx = { I5, I4, I3, I2, I1, I0 };
-output O = lutdata[idx];
+output O;
+assign O = lutdata[idx];
 endmodule
 
 module MUXCY(O, CI, DI, S);
 input CI, DI, S;
-output O = S ? CI : DI;
+output O;
+assign O = S ? CI : DI;
 endmodule
 
 module MUXF7(O, I0, I1, S);
 input I0, I1, S;
-output O = S ? I1 : I0;
+output O;
+assign O = S ? I1 : I0;
 endmodule
 
 module VCC(P);
-output P = 1;
+output P;
+assign P = 1;
 endmodule
 
 module XORCY(O, CI, LI);
 input CI, LI;
-output O = CI ^ LI;
+output O;
+assign O = CI ^ LI;
 endmodule