3 files changed, 53 insertions, 8 deletions

diff --git a/kernel/modtools.h b/kernel/modtools.h
index 56bc1882..fde59d14 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -59,14 +59,20 @@ struct ModIndex : public RTLIL::Monitor
 
 	void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
 	{
-		for (int i = 0; i < SIZE(sig); i++)
-			database[sigmap(sig[i])].ports.insert(PortInfo(cell, port, i));
+		for (int i = 0; i < SIZE(sig); i++) {
+			RTLIL::SigBit bit = sigmap(sig[i]);
+			if (bit.wire)
+				database[bit].ports.insert(PortInfo(cell, port, i));
+		}
 	}
 
 	void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
 	{
-		for (int i = 0; i < SIZE(sig); i++)
-			database[sigmap(sig[i])].ports.erase(PortInfo(cell, port, i));
+		for (int i = 0; i < SIZE(sig); i++) {
+			RTLIL::SigBit bit = sigmap(sig[i]);
+			if (bit.wire)
+				database[bit].ports.erase(PortInfo(cell, port, i));
+		}
 	}
 
 	const SigBitInfo &info(RTLIL::SigBit bit)
@@ -83,10 +89,11 @@ struct ModIndex : public RTLIL::Monitor
 		for (auto wire : module->wires())
 			if (wire->port_input || wire->port_output)
 				for (int i = 0; i < SIZE(wire); i++) {
-					if (wire->port_input)
-						database[sigmap(RTLIL::SigBit(wire, i))].is_input = true;
-					if (wire->port_output)
-						database[sigmap(RTLIL::SigBit(wire, i))].is_output = true;
+					RTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));
+					if (bit.wire && wire->port_input)
+						database[bit].is_input = true;
+					if (bit.wire && wire->port_output)
+						database[bit].is_output = true;
 				}
 		for (auto cell : module->cells())
 			for (auto &conn : cell->connections())
@@ -137,6 +144,7 @@ struct ModIndex : public RTLIL::Monitor
 	{
 		if (auto_reload_module)
 			reload_module();
+
 		auto it = database.find(sigmap(bit));
 		if (it == database.end())
 			return nullptr;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 792474af..8ff56451 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1071,6 +1071,36 @@ void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
 		log_abort();
 }
 
+void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
+{
+	log_assert(wires_[w1->name] == w1);
+	log_assert(wires_[w2->name] == w2);
+	log_assert(refcount_wires_ == 0);
+
+	wires_.erase(w1->name);
+	wires_.erase(w2->name);
+
+	std::swap(w1->name, w2->name);
+
+	wires_[w1->name] = w1;
+	wires_[w2->name] = w2;
+}
+
+void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
+{
+	log_assert(cells_[c1->name] == c1);
+	log_assert(cells_[c2->name] == c2);
+	log_assert(refcount_cells_ == 0);
+
+	cells_.erase(c1->name);
+	cells_.erase(c2->name);
+
+	std::swap(c1->name, c2->name);
+
+	cells_[c1->name] = c1;
+	cells_[c2->name] = c2;
+}
+
 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
 {
 	if (a->port_id && !b->port_id)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8dfcbcaa..8ec59941 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -590,6 +590,10 @@ public:
 	std::vector<RTLIL::Wire*> selected_wires() const;
 	std::vector<RTLIL::Cell*> selected_cells() const;
 
+	template<typename T> bool selected(T *member) const {
+		return design->selected_member(name, member->name);
+	}
+
 	RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; }
 	RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; }
 
@@ -604,6 +608,9 @@ public:
 	void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
 	void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
 
+	void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
+	void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
+
 	RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
 	RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);