5 files changed, 77 insertions, 3 deletions
diff --git a/manual/APPNOTE_011_Design_Investigation.tex b/manual/APPNOTE_011_Design_Investigation.tex
index 2e55b5a0..116c42e1 100644
--- a/manual/APPNOTE_011_Design_Investigation.tex
+++ b/manual/APPNOTE_011_Design_Investigation.tex
@@ -654,11 +654,60 @@ See {\tt help select} for a complete list of actions available in selections.
 
 \subsection{Storing and recalling selections}
 
-\FIXME{}
+The current selection can be stored in memory with the command {\tt select -set
+<name>}. It can later be recalled using {\tt select @<name>}. In fact, the {\tt
+@<name>} expression pushes the stored selection on the stack maintained by the
+{\tt select} command. So for example
+
+\begin{verbatim}
+select @foo @bar %i
+\end{verbatim}
+
+will select the intersection between the stored selections {\tt foo} and {\tt bar}.
+
+\medskip
+
+In larger investigation efforts it is highly recommended to maintain a script that
+sets up relevant selections, so they can easily be recalled, for example when
+Yosys needs to be re-run after a design or source code change.
+
+The {\tt history} command can be used to list all recent interactive commands.
+A feature that can be useful to create such a script from the commands used in
+an interactive session.
 
 \section{Advanced investigation techniques}
 \label{poke}
 
+When working with very large modules, it is often not enough to just select the
+interesting part of the module. Instead it can be useful to extract the
+interesting part of the circuit into a separate module. This can for example be
+useful if one wants to run a series of synthesis commands on the critical part
+of the module and wants to carefully read all the debug output created by the
+commands in order to spot a problem. This kind of troubleshooting is much easier
+if the circuit under investigation is encapsulated in a separate module.
+
+\begin{figure}[b]
+\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_00.pdf} \\ \centerline{\tt memdemo} \vskip1em
+
+\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_01.pdf} \\ \centerline{\tt scramble} \vskip1em
+
+\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_02.pdf} \\ \centerline{\tt outstage} \vskip1em
+
+\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{APPNOTE_011_Design_Investigation/submod_03.pdf} \\ \centerline{\tt selstage} \vskip1em
+
+\begin{lstlisting}[basicstyle=\ttfamily\scriptsize]
+select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
+select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d
+select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d
+submod -name scramble @scramble
+submod -name outstage @outstage
+submod -name selstage @selstage
+\end{lstlisting}
+\caption{The circuit from Fig.~\ref{memdemo_src} and \ref{memdemo_00} broken up using {\tt submod}}
+\label{submod}
+\end{figure}
+
+
 \FIXME{} --- submod, eval, sat
 
 \section{Conclusion}
diff --git a/manual/APPNOTE_011_Design_Investigation/.gitignore b/manual/APPNOTE_011_Design_Investigation/.gitignore
index 6df5200c..85e44618 100644
--- a/manual/APPNOTE_011_Design_Investigation/.gitignore
+++ b/manual/APPNOTE_011_Design_Investigation/.gitignore
@@ -13,3 +13,7 @@ sumprod_04.dot
 sumprod_05.dot
 memdemo_00.dot
 memdemo_01.dot
+submod_00.dot
+submod_01.dot
+submod_02.dot
+submod_03.dot
diff --git a/manual/APPNOTE_011_Design_Investigation/make.sh b/manual/APPNOTE_011_Design_Investigation/make.sh
index d0d20b2e..a88f642d 100644
--- a/manual/APPNOTE_011_Design_Investigation/make.sh
+++ b/manual/APPNOTE_011_Design_Investigation/make.sh
@@ -11,7 +11,8 @@
 ../../yosys -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
 ../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
 ../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
-sed -i '/^label=/ d;' example_*.dot splice.dot cmos_*.dot sumprod_*.dot memdemo_*.dot
+../../yosys submod.ys
+sed -i '/^label=/ d;' example_*.dot splice.dot cmos_*.dot sumprod_*.dot memdemo_*.dot submod_*.dot
 dot -Tpdf -o example_00.pdf example_00.dot
 dot -Tpdf -o example_01.pdf example_01.dot
 dot -Tpdf -o example_02.pdf example_02.dot
@@ -27,3 +28,7 @@ dot -Tpdf -o sumprod_04.pdf sumprod_04.dot
 dot -Tpdf -o sumprod_05.pdf sumprod_05.dot
 dot -Tpdf -o memdemo_00.pdf memdemo_00.dot
 dot -Tpdf -o memdemo_01.pdf memdemo_01.dot
+dot -Tpdf -o submod_00.pdf submod_00.dot
+dot -Tpdf -o submod_01.pdf submod_01.dot
+dot -Tpdf -o submod_02.pdf submod_02.dot
+dot -Tpdf -o submod_03.pdf submod_03.dot
diff --git a/manual/APPNOTE_011_Design_Investigation/memdemo.v b/manual/APPNOTE_011_Design_Investigation/memdemo.v
index babc24e2..b39564dd 100644
--- a/manual/APPNOTE_011_Design_Investigation/memdemo.v
+++ b/manual/APPNOTE_011_Design_Investigation/memdemo.v
@@ -11,7 +11,7 @@ reg [3:0] mem [0:3];
 always @(posedge clk) begin
     for (i = 0; i < 4; i = i+1)
         mem[i] <= mem[(i+1) % 4] + mem[(i+2) % 4];
-    { s2, s1 } = d ? { s1, s2 } ^ d : 0;
+    { s2, s1 } = d ? { s1, s2 } ^ d : 4'b0;
     mem[s1] <= d;
     y <= mem[s2];
 end
diff --git a/manual/APPNOTE_011_Design_Investigation/submod.ys b/manual/APPNOTE_011_Design_Investigation/submod.ys
new file mode 100644
index 00000000..29ad6107
--- /dev/null
+++ b/manual/APPNOTE_011_Design_Investigation/submod.ys
@@ -0,0 +1,16 @@
+read_verilog memdemo.v
+proc; opt; memory; opt
+
+cd memdemo
+select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
+select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d
+select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d
+submod -name scramble @scramble
+submod -name outstage @outstage
+submod -name selstage @selstage
+
+cd ..
+show -format dot -prefix submod_00 memdemo
+show -format dot -prefix submod_01 scramble
+show -format dot -prefix submod_02 outstage
+show -format dot -prefix submod_03 selstage