diff options
Diffstat (limited to 'passes/abc/abc.cc')
| -rw-r--r-- | passes/abc/abc.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 2fd3334c..a51557a4 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -459,6 +459,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Wire *wire = new RTLIL::Wire; wire->name = remap_name(w->name); module->wires[wire->name] = wire; + design->select(module, wire); } std::map<std::string, int> cell_stats; @@ -488,6 +489,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]); cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]); module->cells[cell->name] = cell; + design->select(module, cell); continue; } if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") { @@ -498,6 +500,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks[0].wire->name)]); cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]); module->cells[cell->name] = cell; + design->select(module, cell); continue; } if (c->type == "\\MUX") { @@ -509,6 +512,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks[0].wire->name)]); cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]); module->cells[cell->name] = cell; + design->select(module, cell); continue; } assert(0); @@ -532,6 +536,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto &conn : c->connections) cell->connections[conn.first] = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]); module->cells[cell->name] = cell; + design->select(module, cell); } } |