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-rw-r--r--passes/cmds/Makefile.inc1
-rw-r--r--passes/cmds/connect.cc185
-rw-r--r--passes/cmds/splitnets.cc125
3 files changed, 282 insertions, 29 deletions
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 24d6075b..9e96ff36 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -4,6 +4,7 @@ OBJS += passes/cmds/design.o
OBJS += passes/cmds/select.o
OBJS += passes/cmds/show.o
OBJS += passes/cmds/rename.o
+OBJS += passes/cmds/connect.o
OBJS += passes/cmds/scatter.o
OBJS += passes/cmds/splitnets.o
OBJS += passes/cmds/stat.o
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
new file mode 100644
index 00000000..7a54e8dc
--- /dev/null
+++ b/passes/cmds/connect.cc
@@ -0,0 +1,185 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "kernel/sigtools.h"
+#include "kernel/celltypes.h"
+#include "kernel/log.h"
+
+static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, RTLIL::SigSpec &sig)
+{
+ CellTypes ct(design);
+
+ RTLIL::Wire *dummy_wire = module->new_wire(sig.width, NEW_ID);
+
+ for (auto &it : module->cells)
+ for (auto &port : it.second->connections)
+ if (ct.cell_output(it.second->type, port.first))
+ sigmap(port.second).replace(sig, dummy_wire, &port.second);
+
+ for (auto &conn : module->connections)
+ sigmap(conn.first).replace(sig, dummy_wire, &conn.first);
+}
+
+struct ConnectPass : public Pass {
+ ConnectPass() : Pass("connect", "create or remove connections") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
+ log("\n");
+ log("Create a connection. This is equivialent to adding the statement 'assign\n");
+ log("<lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing\n");
+ log("drivers for <lhs-expr> are unconnected. This can be overwritten by using\n");
+ log("the -nounset option.\n");
+ log("\n");
+ log("\n");
+ log(" connect [-nomap] -unset <expr>\n");
+ log("\n");
+ log("Unconnect all existing drivers for the specified expression.\n");
+ log("\n");
+ log("\n");
+ log(" connect [-nomap] -port <cell> <port> <expr>\n");
+ log("\n");
+ log("Connect the specified cell port to the specified cell port.\n");
+ log("\n");
+ log("\n");
+ log("Per default signal alias names are resolved and all signal names are mapped\n");
+ log("the the signal name of the primary driver. Using the -nomap option deactivates\n");
+ log("this behavior.\n");
+ log("\n");
+ log("The connect command operates in one module only. Either only one module must\n");
+ log("be selected or an active module must be set using the 'cd' command.\n");
+ log("\n");
+ log("This command does not operate on module with processes.\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ RTLIL::Module *module = NULL;
+ for (auto &it : design->modules) {
+ if (!design->selected(it.second))
+ continue;
+ if (module != NULL)
+ log_cmd_error("Multiple modules selected: %s, %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.first));
+ module = it.second;
+ }
+ if (module == NULL)
+ log_cmd_error("No modules selected.\n");
+ if (!module->processes.empty())
+ log_cmd_error("Found processes in selected module.\n");
+
+ bool flag_nounset = false, flag_nomap = false;
+ std::string set_lhs, set_rhs, unset_expr;
+ std::string port_cell, port_port, port_expr;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ std::string arg = args[argidx];
+ if (arg == "-nounset") {
+ flag_nounset = true;
+ continue;
+ }
+ if (arg == "-nomap") {
+ flag_nomap = true;
+ continue;
+ }
+ if (arg == "-set" && argidx+2 < args.size()) {
+ set_lhs = args[++argidx];
+ set_rhs = args[++argidx];
+ continue;
+ }
+ if (arg == "-unset" && argidx+1 < args.size()) {
+ unset_expr = args[++argidx];
+ continue;
+ }
+ if (arg == "-port" && argidx+3 < args.size()) {
+ port_cell = args[++argidx];
+ port_port = args[++argidx];
+ port_expr = args[++argidx];
+ continue;
+ }
+ break;
+ }
+
+ SigMap sigmap;
+ if (!flag_nomap)
+ for (auto &it : module->connections) {
+ std::vector<RTLIL::SigBit> lhs = it.first.to_sigbit_vector();
+ std::vector<RTLIL::SigBit> rhs = it.first.to_sigbit_vector();
+ for (size_t i = 0; i < lhs.size(); i++)
+ if (rhs[i].wire != NULL)
+ sigmap.add(lhs[i], rhs[i]);
+ }
+
+ if (!set_lhs.empty())
+ {
+ if (!unset_expr.empty() || !port_cell.empty())
+ log_cmd_error("Cant use -set together with -unset and/or -port.\n");
+
+ RTLIL::SigSpec sig_lhs, sig_rhs;
+ if (!RTLIL::SigSpec::parse(sig_lhs, module, set_lhs))
+ log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs.c_str());
+ if (!RTLIL::SigSpec::parse_rhs(sig_lhs, sig_rhs, module, set_rhs))
+ log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs.c_str());
+
+ sigmap.apply(sig_lhs);
+ sigmap.apply(sig_rhs);
+
+ if (!flag_nounset)
+ unset_drivers(design, module, sigmap, sig_lhs);
+
+ module->connections.push_back(RTLIL::SigSig(sig_lhs, sig_rhs));
+ }
+ else
+ if (!unset_expr.empty())
+ {
+ if (!port_cell.empty() || flag_nounset)
+ log_cmd_error("Cant use -unset together with -port and/or -nounset.\n");
+
+ RTLIL::SigSpec sig;
+ if (!RTLIL::SigSpec::parse(sig, module, unset_expr))
+ log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr.c_str());
+
+ sigmap.apply(sig);
+ unset_drivers(design, module, sigmap, sig);
+ }
+ else
+ if (!port_cell.empty())
+ {
+ if (flag_nounset)
+ log_cmd_error("Cant use -port together with -nounset.\n");
+
+ if (module->cells.count(RTLIL::escape_id(port_cell)) == 0)
+ log_cmd_error("Can't find cell %s.\n", port_cell.c_str());
+
+ RTLIL::SigSpec sig;
+ if (!RTLIL::SigSpec::parse(sig, module, port_expr))
+ log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
+
+ module->cells.at(RTLIL::escape_id(port_cell))->connections[RTLIL::escape_id(port_port)] = sigmap(sig);
+ }
+ else
+ log_cmd_error("Expected -set, -unset, or -port.\n");
+ }
+} ConnectPass;
+
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 628e87db..68e1edd1 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -24,16 +24,48 @@
struct SplitnetsWorker
{
- std::map<RTLIL::Wire*, std::vector<RTLIL::Wire*>> splitmap;
+ std::map<RTLIL::Wire*, std::vector<RTLIL::SigBit>> splitmap;
+
+ void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format)
+ {
+ RTLIL::Wire *new_wire = new RTLIL::Wire;
+
+ new_wire->port_id = wire->port_id;
+ new_wire->port_input = wire->port_input;
+ new_wire->port_output = wire->port_output;
+ new_wire->name = wire->name;
+ new_wire->width = width;
+
+ if (format.size() > 0)
+ new_wire->name += format.substr(0, 1);
+
+ if (width > 1) {
+ new_wire->name += stringf("%d", offset+width-1);
+ if (format.size() > 2)
+ new_wire->name += format.substr(2, 1);
+ else
+ new_wire->name += ":";
+ }
+
+ new_wire->name += stringf("%d", offset);
+
+ if (format.size() > 1)
+ new_wire->name += format.substr(1, 1);
+
+ while (module->count_id(new_wire->name) > 0)
+ new_wire->name = new_wire->name + "_";
+ module->add(new_wire);
+
+ std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
+ splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end());
+ }
void operator()(RTLIL::SigSpec &sig)
{
sig.expand();
for (auto &c : sig.chunks)
- if (splitmap.count(c.wire) > 0) {
- c.wire = splitmap.at(c.wire).at(c.offset);
- c.offset = 0;
- }
+ if (splitmap.count(c.wire) > 0)
+ c = splitmap.at(c.wire).at(c.offset);
sig.optimize();
}
};
@@ -48,19 +80,25 @@ struct SplitnetsPass : public Pass {
log("\n");
log("This command splits multi-bit nets into single-bit nets.\n");
log("\n");
- log(" -format char1[char2]\n");
+ log(" -format char1[char2[char3]]\n");
log(" the first char is inserted between the net name and the bit index, the\n");
log(" second char is appended to the netname. e.g. -format () creates net\n");
- log(" names like 'mysignal(42)'. the default is '[]'.\n");
+ log(" names like 'mysignal(42)'. the 3rd character is the range seperation\n");
+ log(" character when creating multi-bit wires. the default is '[]:'.\n");
log("\n");
log(" -ports\n");
log(" also split module ports. per default only internal signals are split.\n");
log("\n");
+ log(" -driver\n");
+ log(" don't blindly split nets in individual bits. instead look at the driver\n");
+ log(" and split nets so that no driver drives only part of a net.\n");
+ log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
bool flag_ports = false;
- std::string format = "[]";
+ bool flag_driver = false;
+ std::string format = "[]:";
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -73,6 +111,10 @@ struct SplitnetsPass : public Pass {
flag_ports = true;
continue;
}
+ if (args[argidx] == "-driver") {
+ flag_driver = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -85,30 +127,55 @@ struct SplitnetsPass : public Pass {
SplitnetsWorker worker;
- for (auto &w : module->wires) {
- RTLIL::Wire *wire = w.second;
- if (wire->width > 1 && (wire->port_id == 0 || flag_ports))
- worker.splitmap[wire] = std::vector<RTLIL::Wire*>();
- }
+ if (flag_driver)
+ {
+ CellTypes ct(design);
+
+ std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
+
+ for (auto &c : module->cells)
+ for (auto &p : c.second->connections)
+ {
+ if (!ct.cell_known(c.second->type))
+ continue;
+ if (!ct.cell_output(c.second->type, p.first))
+ continue;
- for (auto &it : worker.splitmap)
- for (int i = 0; i < it.first->width; i++) {
- RTLIL::Wire *wire = new RTLIL::Wire;
- wire->port_id = it.first->port_id;
- wire->port_input = it.first->port_input;
- wire->port_output = it.first->port_output;
- wire->name = it.first->name;
- if (format.size() > 0)
- wire->name += format.substr(0, 1);
- wire->name += stringf("%d", i);
- if (format.size() > 0)
- wire->name += format.substr(1);
- while (module->count_id(wire->name) > 0)
- wire->name = wire->name + "_";
- module->add(wire);
- it.second.push_back(wire);
+ RTLIL::SigSpec sig = p.second.optimized();
+ for (auto &chunk : sig.chunks) {
+ if (chunk.wire == NULL)
+ continue;
+ if (chunk.wire->port_id == 0 || flag_ports) {
+ if (chunk.offset != 0)
+ split_wires_at[chunk.wire].insert(chunk.offset);
+ if (chunk.offset + chunk.width < chunk.wire->width)
+ split_wires_at[chunk.wire].insert(chunk.offset + chunk.width);
+ }
+ }
}
+ for (auto &it : split_wires_at) {
+ int cursor = 0;
+ for (int next_cursor : it.second) {
+ worker.append_wire(module, it.first, cursor, next_cursor - cursor, format);
+ cursor = next_cursor;
+ }
+ worker.append_wire(module, it.first, cursor, it.first->width - cursor, format);
+ }
+ }
+ else
+ {
+ for (auto &w : module->wires) {
+ RTLIL::Wire *wire = w.second;
+ if (wire->width > 1 && (wire->port_id == 0 || flag_ports))
+ worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
+ }
+
+ for (auto &it : worker.splitmap)
+ for (int i = 0; i < it.first->width; i++)
+ worker.append_wire(module, it.first, i, 1, format);
+ }
+
module->rewrite_sigspecs(worker);
for (auto &it : worker.splitmap) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-29 09:45:12 +0000