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-rw-r--r--passes/sat/example.ys16
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/sat/example.ys b/passes/sat/example.ys
index c532c1fb..11f5b924 100644
--- a/passes/sat/example.ys
+++ b/passes/sat/example.ys
@@ -2,12 +2,12 @@
read_verilog example.v
proc; opt_clean
-sat_solve -set y 1'b1 example001
-sat_solve -set y 1'b1 example002
-sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
-sat_solve -set y 1'b1 example004
-sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
-
-sat_solve -prove y 1'b0 -show rst,counter,y example004
-sat_solve -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004
+sat -set y 1'b1 example001
+sat -set y 1'b1 example002
+sat -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
+sat -set y 1'b1 example004
+sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
+
+sat -prove y 1'b0 -show rst,counter,y example004
+sat -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004