diff options
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/freduce.cc | 4 | ||||
| -rw-r--r-- | passes/sat/miter.cc | 12 | ||||
| -rw-r--r-- | passes/sat/share.cc | 26 |
3 files changed, 21 insertions, 21 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index d4b7b5c1..ac041564 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -707,7 +707,7 @@ struct FreduceWorker log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit)); RTLIL::Cell *drv = drivers.at(grp[i].bit).first; - RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID); for (auto &port : drv->connections) if (ct.cell_output(drv->type, port.first)) sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); @@ -716,7 +716,7 @@ struct FreduceWorker { if (inv_sig.width == 0) { - inv_sig = module->new_wire(1, NEW_ID); + inv_sig = module->addWire(NEW_ID); RTLIL::Cell *inv_cell = new RTLIL::Cell; inv_cell->name = NEW_ID; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 0ef9e9aa..6e57fceb 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -164,7 +164,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, if (flag_ignore_gold_x) { - RTLIL::SigSpec gold_x = miter_module->new_wire(w2_gold->width, NEW_ID); + RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width); for (int i = 0; i < w2_gold->width; i++) { RTLIL::Cell *eqx_cell = new RTLIL::Cell; eqx_cell->name = NEW_ID; @@ -180,8 +180,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, miter_module->add(eqx_cell); } - RTLIL::SigSpec gold_masked = miter_module->new_wire(w2_gold->width, NEW_ID); - RTLIL::SigSpec gate_masked = miter_module->new_wire(w2_gate->width, NEW_ID); + RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width); + RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width); RTLIL::Cell *or_gold_cell = new RTLIL::Cell; or_gold_cell->name = NEW_ID; @@ -219,7 +219,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, eq_cell->parameters["\\B_SIGNED"] = 0; eq_cell->connections["\\A"] = gold_masked; eq_cell->connections["\\B"] = gate_masked; - eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID); + eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); this_condition = eq_cell->connections["\\Y"]; miter_module->add(eq_cell); } @@ -235,7 +235,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, eq_cell->parameters["\\B_SIGNED"] = 0; eq_cell->connections["\\A"] = w2_gold; eq_cell->connections["\\B"] = w2_gate; - eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID); + eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); this_condition = eq_cell->connections["\\Y"]; miter_module->add(eq_cell); } @@ -261,7 +261,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; reduce_cell->connections["\\A"] = all_conditions; - reduce_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID); + reduce_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); all_conditions = reduce_cell->connections["\\Y"]; miter_module->add(reduce_cell); } diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 852d8078..42e59c47 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -276,11 +276,11 @@ struct ShareWorker int a_width = std::max(a1.width, a2.width); int y_width = std::max(y1.width, y2.width); - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); - RTLIL::Wire *y = module->new_wire(y_width, NEW_ID); + RTLIL::Wire *y = module->addWire(NEW_ID, y_width); RTLIL::Cell *supercell = new RTLIL::Cell; supercell->name = NEW_ID; @@ -375,24 +375,24 @@ struct ShareWorker { a_width = std::max(y_width, a_width); - if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->new_wire(y1.width, NEW_ID), true)->connections.at("\\Y"); - if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->new_wire(y2.width, NEW_ID), true)->connections.at("\\Y"); + if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.width), true)->connections.at("\\Y"); + if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.width), true)->connections.at("\\Y"); - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y"); - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y"); + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); } else { - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); } - if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); - if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); + if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); + if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); - RTLIL::Wire *y = module->new_wire(y_width, NEW_ID); + RTLIL::Wire *y = module->addWire(NEW_ID, y_width); RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); supercell->parameters["\\A_SIGNED"] = a_signed; @@ -617,7 +617,7 @@ struct ShareWorker RTLIL::SigSpec make_cell_activation_logic(const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &activation_patterns) { - RTLIL::Wire *all_cases_wire = module->new_wire(0, NEW_ID); + RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); for (auto &p : activation_patterns) { all_cases_wire->width++; module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1)); |