diff options
Diffstat (limited to 'passes')
45 files changed, 505 insertions, 505 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index e21be30b..2d921b7b 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -69,8 +69,8 @@ static RTLIL::SigSpec clk_sig; static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1) { - assert(sig.__width == 1); - assert(sig.__chunks.size() == 1); + assert(sig.size() == 1); + assert(sig.chunks().size() == 1); assign_map.apply(sig); @@ -105,7 +105,7 @@ static void mark_port(RTLIL::SigSpec sig) { assign_map.apply(sig); sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire != NULL && signal_map.count(c) > 0) signal_list[signal_map[c]].is_port = true; } @@ -124,7 +124,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) RTLIL::SigSpec sig_q = cell->connections["\\Q"]; if (keepff) - for (auto &c : sig_q.__chunks) + for (auto &c : sig_q.chunks()) if (c.wire != NULL) c.wire->attributes["\\keep"] = 1; @@ -300,8 +300,8 @@ static void handle_loops() for (auto &edge_it : edges) { int id2 = edge_it.first; - RTLIL::Wire *w1 = signal_list[id1].sig.__chunks[0].wire; - RTLIL::Wire *w2 = signal_list[id2].sig.__chunks[0].wire; + RTLIL::Wire *w1 = signal_list[id1].sig.chunks()[0].wire; + RTLIL::Wire *w2 = signal_list[id2].sig.chunks()[0].wire; if (w1 != NULL) continue; else if (w2 == NULL) @@ -469,7 +469,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1)); } - if (dff_mode && clk_sig.__width == 0) + if (dff_mode && clk_sig.size() == 0) { int best_dff_counter = 0; std::map<std::pair<bool, RTLIL::SigSpec>, int> dff_counters; @@ -490,13 +490,13 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } if (dff_mode || !clk_str.empty()) { - if (clk_sig.__width == 0) + if (clk_sig.size() == 0) log("No (matching) clock domain found. Not extracting any FF cells.\n"); else log("Found (matching) %s clock domain: %s\n", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig)); } - if (clk_sig.__width != 0) + if (clk_sig.size() != 0) mark_port(clk_sig); std::vector<RTLIL::Cell*> cells; @@ -552,10 +552,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.sig)); for (auto &si : signal_list) { - assert(si.sig.__width == 1 && si.sig.__chunks.size() == 1); - if (si.sig.__chunks[0].wire == NULL) { + assert(si.sig.size() == 1 && si.sig.chunks().size() == 1); + if (si.sig.chunks()[0].wire == NULL) { fprintf(f, ".names n%d\n", si.id); - if (si.sig.__chunks[0].data.bits[0] == RTLIL::State::S1) + if (si.sig.chunks()[0].data.bits[0] == RTLIL::State::S1) fprintf(f, "1\n"); } } @@ -716,15 +716,15 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); module->connections.push_back(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); - conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); module->connections.push_back(conn); continue; } @@ -732,8 +732,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_INV_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -742,9 +742,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_" + c->type.substr(1) + "_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].__chunks[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -753,21 +753,21 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_MUX_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].__chunks[0].wire->name)]); - cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].__chunks[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]); + cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks()[0].wire->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; } if (c->type == "\\DFF") { - log_assert(clk_sig.__width == 1); + log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].__chunks[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].__chunks[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -784,18 +784,18 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.__chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.chunks()[0].wire->name)]); conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); module->connections.push_back(conn); continue; } if (c->type == "\\_dff_") { - log_assert(clk_sig.__width == 1); + log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].__chunks[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].__chunks[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -807,7 +807,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell->name = remap_name(c->name); for (auto &conn : c->connections) { RTLIL::SigSpec newsig; - for (auto &c : conn.second.__chunks) { + for (auto &c : conn.second.chunks()) { if (c.width == 0) continue; assert(c.width == 1); @@ -822,9 +822,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto conn : mapped_mod->connections) { if (!conn.first.is_fully_const()) - conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.__chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks()[0].wire->name)]); if (!conn.second.is_fully_const()) - conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.__chunks[0].wire->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks()[0].wire->name)]); module->connections.push_back(conn); } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 65ebe541..47fa0f82 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -177,10 +177,10 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) } input_sig.append(wire); } - output_sig = input_sig.extract(input_sig.__width-1, 1); - input_sig = input_sig.extract(0, input_sig.__width-1); + output_sig = input_sig.extract(input_sig.size()-1, 1); + input_sig = input_sig.extract(0, input_sig.size()-1); - if (input_sig.__width == 0) { + if (input_sig.size() == 0) { RTLIL::State state = RTLIL::State::Sa; while (1) { if (!read_next_line(buffer, buffer_size, line_count, f)) @@ -218,8 +218,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$lut"; - cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.__width); - cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); + cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); cell->connections["\\I"] = input_sig; cell->connections["\\O"] = output_sig; lutptr = &cell->parameters.at("\\LUT"); diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index f8f9e059..dcd5fc96 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.__width); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); for (auto &it : module->cells) for (auto &port : it.second->connections) diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 426d2b62..6cb2a892 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -90,7 +90,7 @@ struct ConnwrappersWorker continue; int inner_width = cell->parameters.at(decl.widthparam).as_int(); - int outer_width = conn.second.__width; + int outer_width = conn.second.size(); bool is_signed = decl.signparam.empty() ? decl.is_signed : cell->parameters.at(decl.signparam).as_bool(); if (inner_width >= outer_width) @@ -124,20 +124,20 @@ struct ConnwrappersWorker int extend_width = 0; RTLIL::SigBit extend_bit = is_signed ? sigbits[i] : RTLIL::SigBit(RTLIL::State::S0); - while (extend_width < extend_sig.__width && i + extend_width + 1 < sigbits.size() && + while (extend_width < extend_sig.size() && i + extend_width + 1 < sigbits.size() && sigbits[i + extend_width + 1] == extend_bit) extend_width++; if (extend_width == 0) continue; - if (old_sig.__width == 0) + if (old_sig.size() == 0) old_sig = conn.second; conn.second.replace(i+1, extend_sig.extract(0, extend_width)); i += extend_width; } - if (old_sig.__width) + if (old_sig.size()) log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second)); } diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 16828e4f..c5aa196c 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -28,7 +28,7 @@ struct DeleteWireWorker void operator()(RTLIL::SigSpec &sig) { sig.optimize(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index da36c782..d5976dcb 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -53,7 +53,7 @@ struct ScatterPass : public Pass { { RTLIL::Wire *wire = new RTLIL::Wire; wire->name = NEW_ID; - wire->width = p.second.__width; + wire->width = p.second.size(); mod_it.second->add(wire); if (ct.cell_output(c.second->type, p.first)) { diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index d668bc3a..49e79bd4 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -191,7 +191,7 @@ struct SccWorker nextsig.sort_and_unify(); sig = prevsig.extract(nextsig); - for (auto &chunk : sig.__chunks) + for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) sel.selected_members[module->name].insert(chunk.wire->name); } diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 068162eb..123483a3 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -415,7 +415,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v include_match: is_input = mode == 'x' || ct.cell_input(cell.second->type, conn.first); is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first); - for (auto &chunk : conn.second.__chunks) + for (auto &chunk : conn.second.chunks()) if (chunk.wire != NULL) { if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && lhs.selected_members[mod->name].count(cell.first) == 0) if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input)) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 3a99c0ce..7558a4e9 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -48,7 +48,7 @@ struct SetundefWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1) c.data.bits.at(0) = next_bit(); sig.optimize(); @@ -141,7 +141,7 @@ struct SetundefPass : public Pass { undriven_signals.del(sigmap(conn.second)); RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(next_bit()); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 0006a3ff..fde96d53 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -78,7 +78,7 @@ struct ShowWorker std::string nextColor(RTLIL::SigSpec sig, std::string defaultColor) { sig.sort_and_unify(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire != NULL) for (auto &s : color_selections) if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0) @@ -173,13 +173,13 @@ struct ShowWorker { sig.optimize(); - if (sig.__chunks.size() == 0) { + if (sig.chunks().size() == 0) { fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count); return stringf("v%d", single_idx_count++); } - if (sig.__chunks.size() == 1) { - RTLIL::SigChunk &c = sig.__chunks[0]; + if (sig.chunks().size() == 1) { + RTLIL::SigChunk &c = sig.chunks()[0]; if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); @@ -200,10 +200,10 @@ struct ShowWorker { std::string label_string; sig.optimize(); - int pos = sig.__width-1; + int pos = sig.size()-1; int idx = single_idx_count++; - for (int i = int(sig.__chunks.size())-1; i >= 0; i--) { - RTLIL::SigChunk &c = sig.__chunks[i]; + for (int i = int(sig.chunks().size())-1; i >= 0; i--) { + RTLIL::SigChunk &c = sig.chunks()[i]; net = gen_signode_simple(c, false); assert(!net.empty()); if (driver) { @@ -225,9 +225,9 @@ struct ShowWorker if (!port.empty()) { currentColor = xorshift32(currentColor); if (driver) - code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.__width).c_str()); + code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.size()).c_str()); else - code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.__width).c_str()); + code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str()); } if (node != NULL) *node = stringf("x%d", idx); @@ -239,7 +239,7 @@ struct ShowWorker net_conn_map[net].in.insert(port); else net_conn_map[net].out.insert(port); - net_conn_map[net].bits = sig.__width; + net_conn_map[net].bits = sig.size(); net_conn_map[net].color = nextColor(sig, net_conn_map[net].color); } if (node != NULL) @@ -405,7 +405,7 @@ struct ShowWorker code += gen_portbox("", sig, false, &node); fprintf(f, "%s", code.c_str()); net_conn_map[node].out.insert(stringf("p%d", pidx)); - net_conn_map[node].bits = sig.__width; + net_conn_map[node].bits = sig.size(); net_conn_map[node].color = nextColor(sig, net_conn_map[node].color); } @@ -414,7 +414,7 @@ struct ShowWorker code += gen_portbox("", sig, true, &node); fprintf(f, "%s", code.c_str()); net_conn_map[node].in.insert(stringf("p%d", pidx)); - net_conn_map[node].bits = sig.__width; + net_conn_map[node].bits = sig.size(); net_conn_map[node].color = nextColor(sig, net_conn_map[node].color); } @@ -427,12 +427,12 @@ struct ShowWorker for (auto &conn : module->connections) { bool found_lhs_wire = false; - for (auto &c : conn.first.__chunks) { + for (auto &c : conn.first.chunks()) { if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) found_lhs_wire = true; } bool found_rhs_wire = false; - for (auto &c : conn.second.__chunks) { + for (auto &c : conn.second.chunks()) { if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) found_rhs_wire = true; } @@ -446,11 +446,11 @@ struct ShowWorker if (left_node[0] == 'x' && right_node[0] == 'x') { currentColor = xorshift32(currentColor); - fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.__width).c_str()); + fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.size()).c_str()); } else { - net_conn_map[right_node].bits = conn.first.__width; + net_conn_map[right_node].bits = conn.first.size(); net_conn_map[right_node].color = nextColor(conn, net_conn_map[right_node].color); - net_conn_map[left_node].bits = conn.first.__width; + net_conn_map[left_node].bits = conn.first.size(); net_conn_map[left_node].color = nextColor(conn, net_conn_map[left_node].color); if (left_node[0] == 'x') { net_conn_map[right_node].in.insert(left_node); diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 80a7f90c..aed9c076 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -52,7 +52,7 @@ struct SpliceWorker RTLIL::SigSpec get_sliced_signal(RTLIL::SigSpec sig) { - if (sig.__width == 0 || sig.is_fully_const()) + if (sig.size() == 0 || sig.is_fully_const()) return sig; if (sliced_signals_cache.count(sig)) @@ -69,15 +69,15 @@ struct SpliceWorker RTLIL::SigSpec new_sig = sig; - if (sig_a.__width != sig.__width) { + if (sig_a.size() != sig.size()) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$slice"; cell->parameters["\\OFFSET"] = offset; - cell->parameters["\\A_WIDTH"] = sig_a.__width; - cell->parameters["\\Y_WIDTH"] = sig.__width; + cell->parameters["\\A_WIDTH"] = sig_a.size(); + cell->parameters["\\Y_WIDTH"] = sig.size(); cell->connections["\\A"] = sig_a; - cell->connections["\\Y"] = module->addWire(NEW_ID, sig.__width); + cell->connections["\\Y"] = module->addWire(NEW_ID, sig.size()); new_sig = cell->connections["\\Y"]; module->add(cell); } @@ -90,7 +90,7 @@ struct SpliceWorker RTLIL::SigSpec get_spliced_signal(RTLIL::SigSpec sig) { - if (sig.__width == 0 || sig.is_fully_const()) + if (sig.size() == 0 || sig.is_fully_const()) return sig; if (spliced_signals_cache.count(sig)) @@ -134,11 +134,11 @@ struct SpliceWorker RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$concat"; - cell->parameters["\\A_WIDTH"] = new_sig.__width; - cell->parameters["\\B_WIDTH"] = sig2.__width; + cell->parameters["\\A_WIDTH"] = new_sig.size(); + cell->parameters["\\B_WIDTH"] = sig2.size(); cell->connections["\\A"] = new_sig; cell->connections["\\B"] = sig2; - cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.__width + sig2.__width); + cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size()); new_sig = cell->connections["\\Y"]; module->add(cell); } diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 7572baa3..8cc6a515 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -63,7 +63,7 @@ struct SplitnetsWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (splitmap.count(c.wire) > 0) c = splitmap.at(c.wire).at(c.offset); sig.optimize(); @@ -144,7 +144,7 @@ struct SplitnetsPass : public Pass { continue; RTLIL::SigSpec sig = p.second.optimized(); - for (auto &chunk : sig.__chunks) { + for (auto &chunk : sig.chunks()) { if (chunk.wire == NULL) continue; if (chunk.wire->port_id == 0 || flag_ports) { diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 523feae9..2ba4c72b 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -56,8 +56,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor)) return false; - for (int i = 0; i < sig_b.__width; i += sig_a.__width) - if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.__width), recursion_monitor)) + for (int i = 0; i < sig_b.size(); i += sig_a.size()) + if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.size()), recursion_monitor)) return false; muxtree_cells.insert(cellport.first); } diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index e4d20077..0dd328db 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -43,7 +43,7 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") - if (cell->connections.at("\\A").__width < 2) + if (cell->connections.at("\\A").size() < 2) return true; RTLIL::SigSpec new_signals; @@ -62,7 +62,7 @@ struct FsmExpand new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"])); new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); - if (new_signals.__width > 3) + if (new_signals.size() > 3) return false; if (cell->connections.count("\\Y") > 0) { @@ -73,7 +73,7 @@ struct FsmExpand new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); } - if (new_signals.__width > 2) + if (new_signals.size() > 2) return false; return true; @@ -145,8 +145,8 @@ struct FsmExpand std::vector<RTLIL::Const> truth_tab; - for (int i = 0; i < (1 << input_sig.__width); i++) { - RTLIL::Const in_val(i, input_sig.__width); + for (int i = 0; i < (1 << input_sig.size()); i++) { + RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; if (cell->connections.count("\\A") > 0) A = assign_map(cell->connections["\\A"]); @@ -166,17 +166,17 @@ struct FsmExpand FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - fsm_data.num_inputs += input_sig.__width; + fsm_data.num_inputs += input_sig.size(); fsm_cell->connections["\\CTRL_IN"].append(input_sig); - fsm_data.num_outputs += output_sig.__width; + fsm_data.num_outputs += output_sig.size(); fsm_cell->connections["\\CTRL_OUT"].append(output_sig); std::vector<FsmData::transition_t> new_transition_table; for (auto &tr : fsm_data.transition_table) { - for (int i = 0; i < (1 << input_sig.__width); i++) { + for (int i = 0; i < (1 << input_sig.size()); i++) { FsmData::transition_t new_tr = tr; - RTLIL::Const in_val(i, input_sig.__width); + RTLIL::Const in_val(i, input_sig.size()); RTLIL::Const out_val = truth_tab[i]; RTLIL::SigSpec ctrl_in = new_tr.ctrl_in; RTLIL::SigSpec ctrl_out = new_tr.ctrl_out; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index c0b5857f..701b09bd 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -36,7 +36,7 @@ static SigSet<sig2driver_entry_t> sig2driver, sig2trigger; static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL) { - sig.extend(dff_out.__width, false); + sig.extend(dff_out.size(), false); if (sig == dff_out) return true; @@ -44,10 +44,10 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL assign_map.apply(sig); if (sig.is_fully_const()) { sig.optimize(); - assert(sig.__chunks.size() == 1); - if (states.count(sig.__chunks[0].data) == 0) { + assert(sig.chunks().size() == 1); + if (states.count(sig.chunks()[0].data) == 0) { log(" found state code: %s\n", log_signal(sig)); - states[sig.__chunks[0].data] = -1; + states[sig.chunks()[0].data] = -1; } return true; } @@ -73,14 +73,14 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL break; log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state)); } while (0); - if (ctrl.extract(sig_s).__width == 0) { + if (ctrl.extract(sig_s).size() == 0) { log(" found ctrl input: %s\n", log_signal(sig_s)); ctrl.append(sig_s); } if (!find_states(sig_a, dff_out, ctrl, states)) return false; - for (int i = 0; i < sig_b.__width/sig_a.__width; i++) { - if (!find_states(sig_b.extract(i*sig_a.__width, sig_a.__width), dff_out, ctrl, states)) + for (int i = 0; i < sig_b.size()/sig_a.size(); i++) { + if (!find_states(sig_b.extract(i*sig_a.size(), sig_a.size()), dff_out, ctrl, states)) return false; } } @@ -90,11 +90,11 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec()) { - if (dont_care.__width > 0) { + if (dont_care.size() > 0) { sig.expand(); - for (auto &chunk : sig.__chunks) { + for (auto &chunk : sig.chunks()) { assert(chunk.width == 1); - if (dont_care.extract(chunk).__width > 0) + if (dont_care.extract(chunk).size() > 0) chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); } sig.optimize(); @@ -104,17 +104,17 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no ce.values_map.apply(sig); sig.expand(); - for (auto &chunk : sig.__chunks) { + for (auto &chunk : sig.chunks()) { assert(chunk.width == 1); if (chunk.wire != NULL) chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); } sig.optimize(); - if (sig.__width == 0) + if (sig.size() == 0) return RTLIL::Const(); - assert(sig.__chunks.size() == 1 && sig.__chunks[0].wire == NULL); - return sig.__chunks[0].data; + assert(sig.chunks().size() == 1 && sig.chunks()[0].wire == NULL); + return sig.chunks()[0].data; } static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map<RTLIL::Const, int> &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care) @@ -144,7 +144,7 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d return; } - log_assert(undef.__width > 0); + log_assert(undef.size() > 0); log_assert(ce.stop_signals.check_all(undef)); undef = undef.extract(0, 1); @@ -258,8 +258,8 @@ static void extract_fsm(RTLIL::Wire *wire) // Initialize fsm data struct FsmData fsm_data; - fsm_data.num_inputs = ctrl_in.__width; - fsm_data.num_outputs = ctrl_out.__width; + fsm_data.num_inputs = ctrl_in.size(); + fsm_data.num_outputs = ctrl_out.size(); fsm_data.state_bits = wire->width; fsm_data.reset_state = -1; for (auto &it : states) { @@ -314,7 +314,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = new RTLIL::Wire; unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++); - unconn_wire->width = unconn_sig.__width; + unconn_wire->width = unconn_sig.size(); module->wires[unconn_wire->name] = unconn_wire; port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections[cellport.second]); } @@ -367,7 +367,7 @@ struct FsmExtractPass : public Pass { sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections.count("\\Y") > 0 && - cell_it.second->connections["\\Y"].__width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + cell_it.second->connections["\\Y"].size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index f11d78b3..f8ffee52 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -50,12 +50,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const or_sig.append(RTLIL::SigSpec(state_onehot, 1, in_state)); or_sig.optimize(); - if (or_sig.__width == 0) + if (or_sig.size() == 0) continue; RTLIL::SigSpec and_sig; - if (eq_sig_a.__width > 0) + if (eq_sig_a.size() > 0) { RTLIL::Wire *eq_wire = new RTLIL::Wire; eq_wire->name = NEW_ID; @@ -69,17 +69,17 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const eq_cell->connections["\\Y"] = RTLIL::SigSpec(eq_wire); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.__width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.__width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(eq_cell); and_sig.append(RTLIL::SigSpec(eq_wire)); } - if (or_sig.__width < num_states-int(fullstate_cache.size())) + if (or_sig.size() < num_states-int(fullstate_cache.size())) { - if (or_sig.__width == 1) + if (or_sig.size() == 1) { and_sig.append(or_sig); } @@ -95,7 +95,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const or_cell->connections["\\A"] = or_sig; or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.__width); + or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(or_cell); @@ -103,7 +103,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const } } - switch (and_sig.__width) + switch (and_sig.size()) { case 2: { @@ -138,17 +138,17 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const } } - if (cases_vector.__width > 1) { + if (cases_vector.size() > 1) { RTLIL::Cell *or_cell = new RTLIL::Cell; or_cell->name = NEW_ID; or_cell->type = "$reduce_or"; or_cell->connections["\\A"] = cases_vector; or_cell->connections["\\Y"] = output; or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.__width); + or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(or_cell); - } else if (cases_vector.__width == 1) { + } else if (cases_vector.size() == 1) { module->connections.push_back(RTLIL::SigSig(output, cases_vector)); } else { module->connections.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); @@ -237,8 +237,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.__width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.__width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(eq_cell); } @@ -308,8 +308,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) mux_cell->connections["\\B"] = sig_b; mux_cell->connections["\\S"] = sig_s; mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire); - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.__width); - mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.__width); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); + mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); module->add(mux_cell); } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 6732d2ab..367b38eb 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -33,11 +33,11 @@ struct FsmOpt bool signal_is_unused(RTLIL::SigSpec sig) { - assert(sig.__width == 1); + assert(sig.size() == 1); sig.optimize(); - RTLIL::Wire *wire = sig.__chunks[0].wire; - int bit = sig.__chunks[0].offset; + RTLIL::Wire *wire = sig.chunks()[0].wire; + int bit = sig.chunks()[0].offset; if (!wire || wire->attributes.count("\\unused_bits") == 0) return false; @@ -55,11 +55,11 @@ struct FsmOpt void opt_const_and_unused_inputs() { RTLIL::SigSpec ctrl_in = cell->connections["\\CTRL_IN"]; - std::vector<bool> ctrl_in_used(ctrl_in.__width); + std::vector<bool> ctrl_in_used(ctrl_in.size()); std::vector<FsmData::transition_t> new_transition_table; for (auto &tr : fsm_data.transition_table) { - for (int i = 0; i < ctrl_in.__width; i++) { + for (int i = 0; i < ctrl_in.size(); i++) { RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1); if (ctrl_bit.is_fully_const()) { if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit) @@ -112,8 +112,8 @@ struct FsmOpt { RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"]; - for (int i = 0; i < ctrl_in.__width; i++) - for (int j = i+1; j < ctrl_in.__width; j++) + for (int i = 0; i < ctrl_in.size(); i++) + for (int j = i+1; j < ctrl_in.size(); j++) if (ctrl_in.extract(i, 1) == ctrl_in.extract(j, 1)) { log(" Optimize handling of signal %s that is connected to inputs %d and %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j); @@ -150,8 +150,8 @@ struct FsmOpt RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"]; RTLIL::SigSpec &ctrl_out = cell->connections["\\CTRL_OUT"]; - for (int j = 0; j < ctrl_out.__width; j++) - for (int i = 0; i < ctrl_in.__width; i++) + for (int j = 0; j < ctrl_out.size(); j++) + for (int i = 0; i < ctrl_in.size(); i++) if (ctrl_in.extract(i, 1) == ctrl_out.extract(j, 1)) { log(" Optimize handling of signal %s that is connected to input %d and output %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 6b175306..718b9704 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -143,15 +143,15 @@ struct FsmData log(" Input signals:\n"); RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"]; sig_in.expand(); - for (size_t i = 0; i < sig_in.__chunks.size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_in.__chunks[i])); + for (size_t i = 0; i < sig_in.chunks().size(); i++) + log(" %3zd: %s\n", i, log_signal(sig_in.chunks()[i])); log("\n"); log(" Output signals:\n"); RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"]; sig_out.expand(); - for (size_t i = 0; i < sig_out.__chunks.size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_out.__chunks[i])); + for (size_t i = 0; i < sig_out.chunks().size(); i++) + log(" %3zd: %s\n", i, log_signal(sig_out.chunks()[i])); log("\n"); log(" State encoding:\n"); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 5d9dc18a..90f377e0 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -61,7 +61,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell for (auto &conn : i2.second->connections) { if (conn.first[0] != '$') portnames.insert(conn.first); - portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.__width); + portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size()); } for (auto ¶ : i2.second->parameters) parameters.insert(para.first); @@ -220,7 +220,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Module *mod = design->modules[cell->type]; for (auto &conn : cell->connections) { - int conn_size = conn.second.__width; + int conn_size = conn.second.size(); std::string portname = conn.first; if (portname.substr(0, 1) == "$") { int port_id = atoi(portname.substr(1).c_str()); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index f8f2b596..fa8043c8 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -67,7 +67,7 @@ struct SubmodWorker void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) { - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire != NULL) flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used); } @@ -164,7 +164,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new RTLIL::Cell(*cell); for (auto &conn : new_cell->connections) - for (auto &c : conn.second.__chunks) + for (auto &c : conn.second.chunks()) if (c.wire != NULL) { assert(wire_flags.count(c.wire) > 0); c.wire = wire_flags[c.wire].new_wire; diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6c9e1b77..5f06438f 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -142,16 +142,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_wr_clk_enable.optimize(); sig_wr_clk_polarity.optimize(); - assert(sig_wr_clk.__width == wr_ports); - assert(sig_wr_clk_enable.__width == wr_ports && sig_wr_clk_enable.is_fully_const()); - assert(sig_wr_clk_polarity.__width == wr_ports && sig_wr_clk_polarity.is_fully_const()); - assert(sig_wr_addr.__width == wr_ports * addr_bits); - assert(sig_wr_data.__width == wr_ports * memory->width); - assert(sig_wr_en.__width == wr_ports * memory->width); + assert(sig_wr_clk.size() == wr_ports); + assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); + assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); + assert(sig_wr_addr.size() == wr_ports * addr_bits); + assert(sig_wr_data.size() == wr_ports * memory->width); + assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.__chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0); mem->connections["\\WR_CLK"] = sig_wr_clk; mem->connections["\\WR_ADDR"] = sig_wr_addr; @@ -162,16 +162,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_rd_clk_polarity.optimize(); sig_rd_transparent.optimize(); - assert(sig_rd_clk.__width == rd_ports); - assert(sig_rd_clk_enable.__width == rd_ports && sig_rd_clk_enable.is_fully_const()); - assert(sig_rd_clk_polarity.__width == rd_ports && sig_rd_clk_polarity.is_fully_const()); - assert(sig_rd_addr.__width == rd_ports * addr_bits); - assert(sig_rd_data.__width == rd_ports * memory->width); + assert(sig_rd_clk.size() == rd_ports); + assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); + assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); + assert(sig_rd_addr.size() == rd_ports * addr_bits); + assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.__chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.__chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks()[0].data : RTLIL::Const(0, 0); mem->connections["\\RD_CLK"] = sig_rd_clk; mem->connections["\\RD_ADDR"] = sig_rd_addr; diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 174417bd..8bae24cf 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -34,9 +34,9 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI normalize_sig(module, sig); sig.expand(); - for (size_t i = 0; i < sig.__chunks.size(); i++) + for (size_t i = 0; i < sig.chunks().size(); i++) { - RTLIL::SigChunk &chunk = sig.__chunks[i]; + RTLIL::SigChunk &chunk = sig.chunks()[i]; if (chunk.wire == NULL) continue; @@ -59,11 +59,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI normalize_sig(module, q_norm); RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]); - if (d.__width != 1) + if (d.size() != 1) continue; - assert(d.__chunks.size() == 1); - chunk = d.__chunks[0]; + assert(d.chunks().size() == 1); + chunk = d.chunks()[0]; clk = cell->connections["\\CLK"]; clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; @@ -125,7 +125,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) RTLIL::Wire *wire = new RTLIL::Wire; wire->name = sstr.str(); - wire->width = sig.__width; + wire->width = sig.size(); module->wires[wire->name] = wire; RTLIL::SigSpec newsig(wire); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index b848e09e..e605e6e5 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -68,7 +68,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; - for (int i = 0; i < clocks.__width; i++) { + for (int i = 0; i < clocks.size(); i++) { RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); @@ -89,7 +89,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) cell->name.c_str(), module->name.c_str(), i); return; } - if (refclock.__width == 0) { + if (refclock.size() == 0) { refclock = clocks.extract(i, 1); refclock_pol = clocks_pol.bits[i]; } @@ -277,12 +277,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->connections["\\Y"] = w_seladdr; int wr_offset = 0; - while (wr_offset < wr_en.__width) + while (wr_offset < wr_en.size()) { int wr_width = 1; RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); - while (wr_offset + wr_width < wr_en.__width) { + while (wr_offset + wr_width < wr_en.size()) { RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); if (next_wr_bit != wr_bit) break; diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index e56d14b6..5c349f70 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -116,7 +116,7 @@ struct MemoryShareWorker created_conditions++; } - if (terms.__width > 1) + if (terms.size() > 1) terms = module->ReduceAnd(NEW_ID, terms); return conditions_logic_cache[conditions] = terms; @@ -254,7 +254,7 @@ struct MemoryShareWorker // this is the naive version of the function that does not care about grouping the EN bits. RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits); - RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.__width), inv_mask_bits, do_mask); + RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.size()), inv_mask_bits, do_mask); RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits); return result; } @@ -269,10 +269,10 @@ struct MemoryShareWorker std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::pair<int, std::vector<int>>> groups; RTLIL::SigSpec grouped_bits, grouped_mask_bits; - for (int i = 0; i < bits.__width; i++) { + for (int i = 0; i < bits.size(); i++) { std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]); if (groups.count(key) == 0) { - groups[key].first = grouped_bits.__width; + groups[key].first = grouped_bits.size(); grouped_bits.append_bit(v_bits[i]); grouped_mask_bits.append_bit(v_mask_bits[i]); } @@ -282,7 +282,7 @@ struct MemoryShareWorker std::vector<RTLIL::SigBit> grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits); RTLIL::SigSpec result; - for (int i = 0; i < bits.__width; i++) { + for (int i = 0; i < bits.size(); i++) { std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]); result.append_bit(grouped_result.at(groups.at(key).first)); } @@ -320,7 +320,7 @@ struct MemoryShareWorker // Create the new merged_data signal. - RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.__width); + RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.size()); RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data); RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data)); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 8a097916..68fb2e72 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -106,13 +106,13 @@ static int count_nontrivial_wire_attrs(RTLIL::Wire *w) static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool ®s, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires) { - assert(s1.__width == 1); - assert(s2.__width == 1); - assert(s1.__chunks.size() == 1); - assert(s2.__chunks.size() == 1); + assert(s1.size() == 1); + assert(s2.size() == 1); + assert(s1.chunks().size() == 1); + assert(s2.chunks().size() == 1); - RTLIL::Wire *w1 = s1.__chunks[0].wire; - RTLIL::Wire *w2 = s2.__chunks[0].wire; + RTLIL::Wire *w1 = s1.chunks()[0].wire; + RTLIL::Wire *w2 = s2.chunks()[0].wire; if (w1 == NULL || w2 == NULL) return w2 == NULL; @@ -235,14 +235,14 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } else { s1.expand(); s2.expand(); - assert(s1.__chunks.size() == s2.__chunks.size()); + assert(s1.chunks().size() == s2.chunks().size()); RTLIL::SigSig new_conn; - for (size_t i = 0; i < s1.__chunks.size(); i++) - if (s1.__chunks[i] != s2.__chunks[i]) { - new_conn.first.append(s1.__chunks[i]); - new_conn.second.append(s2.__chunks[i]); + for (size_t i = 0; i < s1.chunks().size(); i++) + if (s1.chunks()[i] != s2.chunks()[i]) { + new_conn.first.append(s1.chunks()[i]); + new_conn.second.append(s2.chunks()[i]); } - if (new_conn.first.__width > 0) { + if (new_conn.first.size() > 0) { new_conn.first.optimize(); new_conn.second.optimize(); used_signals.add(new_conn.first); @@ -258,8 +258,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!used_signals_nodrivers.check_any(sig)) { std::string unused_bits; sig.expand(); - for (size_t i = 0; i < sig.__chunks.size(); i++) { - if (sig.__chunks[i].wire == NULL) + for (size_t i = 0; i < sig.chunks().size(); i++) { + if (sig.chunks()[i].wire == NULL) continue; if (!used_signals_nodrivers.check_any(sig)) { if (!unused_bits.empty()) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index bee86771..1a1f0fe4 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -56,13 +56,13 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) all_signals.del(driven_signals); RTLIL::SigSpec undriven_signals = all_signals.export_all(); - for (auto &c : undriven_signals.__chunks) + for (auto &c : undriven_signals.chunks()) { RTLIL::SigSpec sig = c; if (c.wire->name[0] == '$') sig = used_signals.extract(sig); - if (sig.__width == 0) + if (sig.size() == 0) continue; log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c)); @@ -74,7 +74,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->connections[out_port]; - out_val.extend_u0(Y.__width, false); + out_val.extend_u0(Y.size(), false); log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", cell->type.c_str(), cell->name.c_str(), info.c_str(), @@ -99,11 +99,11 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::SigSpec sig_y = sigmap(cell->connections.at("\\Y")); if (extend_u0) { - sig_a.extend_u0(sig_y.__width, a_signed); - sig_b.extend_u0(sig_y.__width, b_signed); + sig_a.extend_u0(sig_y.size(), a_signed); + sig_b.extend_u0(sig_y.size(), b_signed); } else { - sig_a.extend(sig_y.__width, a_signed); - sig_b.extend(sig_y.__width, b_signed); + sig_a.extend(sig_y.size(), a_signed); + sig_b.extend(sig_y.size(), b_signed); } std::vector<RTLIL::SigBit> bits_a = sig_a, bits_b = sig_b, bits_y = sig_y; @@ -153,7 +153,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com for (auto &it : grouped_bits[i]) { for (auto &bit : it.second) { new_conn.first.append_bit(bit); - new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.__width)); + new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size())); } new_a.append_bit(it.first.first); new_b.append_bit(it.first.second); @@ -162,12 +162,12 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); c->connections["\\A"] = new_a; - c->parameters["\\A_WIDTH"] = new_a.__width; + c->parameters["\\A_WIDTH"] = new_a.size(); c->parameters["\\A_SIGNED"] = false; if (b_name == "\\B") { c->connections["\\B"] = new_b; - c->parameters["\\B_WIDTH"] = new_b.__width; + c->parameters["\\B_WIDTH"] = new_b.size(); c->parameters["\\B_SIGNED"] = false; } @@ -202,7 +202,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (auto &cell_it : module->cells) if (design->selected(module, cell_it.second)) { if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") && - cell_it.second->connections["\\A"].__width == 1 && cell_it.second->connections["\\Y"].__width == 1) + cell_it.second->connections["\\A"].size() == 1 && cell_it.second->connections["\\Y"].size() == 1) invert_map[assign_map(cell_it.second->connections["\\Y"])] = assign_map(cell_it.second->connections["\\A"]); cells.push_back(cell_it.second); } @@ -334,12 +334,12 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); else - replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").__width)); + replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").size())); goto next_cell; } } - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].__width == 1 && + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].size() == 1 && invert_map.count(assign_map(cell->connections["\\A"])) != 0) { replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"]))); goto next_cell; @@ -460,35 +460,35 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec new_a, new_b; a.expand(), b.expand(); - assert(a.__chunks.size() == b.__chunks.size()); - for (size_t i = 0; i < a.__chunks.size(); i++) { - if (a.__chunks[i].wire == NULL && b.__chunks[i].wire == NULL && a.__chunks[i].data.bits[0] != b.__chunks[i].data.bits[0] && - a.__chunks[i].data.bits[0] <= RTLIL::State::S1 && b.__chunks[i].data.bits[0] <= RTLIL::State::S1) { + assert(a.chunks().size() == b.chunks().size()); + for (size_t i = 0; i < a.chunks().size(); i++) { + if (a.chunks()[i].wire == NULL && b.chunks()[i].wire == NULL && a.chunks()[i].data.bits[0] != b.chunks()[i].data.bits[0] && + a.chunks()[i].data.bits[0] <= RTLIL::State::S1 && b.chunks()[i].data.bits[0] <= RTLIL::State::S1) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (a.__chunks[i] == b.__chunks[i]) + if (a.chunks()[i] == b.chunks()[i]) continue; - new_a.append(a.__chunks[i]); - new_b.append(b.__chunks[i]); + new_a.append(a.chunks()[i]); + new_b.append(b.chunks()[i]); } - if (new_a.__width == 0) { + if (new_a.size() == 0) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (new_a.__width < a.__width || new_b.__width < b.__width) { + if (new_a.size() < a.size() || new_b.size() < b.size()) { new_a.optimize(); new_b.optimize(); cell->connections["\\A"] = new_a; cell->connections["\\B"] = new_b; - cell->parameters["\\A_WIDTH"] = new_a.__width; - cell->parameters["\\B_WIDTH"] = new_b.__width; + cell->parameters["\\A_WIDTH"] = new_a.size(); + cell->parameters["\\B_WIDTH"] = new_b.size(); } } @@ -550,10 +550,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec a = assign_map(cell->connections["\\A"]); RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); - if (a.is_fully_const() && a.__width <= 32 && a.as_int() == 1) + if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1) identity_wrt_b = true; - if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1) + if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1) identity_wrt_a = true; } @@ -561,7 +561,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo { RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); - if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1) + if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1) identity_wrt_a = true; } @@ -650,13 +650,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) { RTLIL::SigSpec new_a, new_b, new_s; - int width = cell->connections.at("\\A").__width; + int width = cell->connections.at("\\A").size(); if ((cell->connections.at("\\A").is_fully_undef() && cell->connections.at("\\B").is_fully_undef()) || cell->connections.at("\\S").is_fully_undef()) { replace_cell(module, cell, "mux undef", "\\Y", cell->connections.at("\\A")); goto next_cell; } - for (int i = 0; i < cell->connections.at("\\S").__width; i++) { + for (int i = 0; i < cell->connections.at("\\S").size(); i++) { RTLIL::SigSpec old_b = cell->connections.at("\\B").extract(i*width, width); RTLIL::SigSpec old_s = cell->connections.at("\\S").extract(i, 1); if (old_b.is_fully_undef() || old_s.is_fully_undef()) @@ -665,12 +665,12 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo new_s.append(old_s); } new_a = cell->connections.at("\\A"); - if (new_a.is_fully_undef() && new_s.__width > 0) { - new_a = new_b.extract((new_s.__width-1)*width, width); - new_b = new_b.extract(0, (new_s.__width-1)*width); - new_s = new_s.extract(0, new_s.__width-1); + if (new_a.is_fully_undef() && new_s.size() > 0) { + new_a = new_b.extract((new_s.size()-1)*width, width); + new_b = new_b.extract(0, (new_s.size()-1)*width); + new_s = new_s.extract(0, new_s.size()-1); } - if (new_s.__width == 0) { + if (new_s.size() == 0) { replace_cell(module, cell, "mux undef", "\\Y", new_a); goto next_cell; } @@ -678,13 +678,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo replace_cell(module, cell, "mux undef", "\\Y", new_s); goto next_cell; } - if (cell->connections.at("\\S").__width != new_s.__width) { + if (cell->connections.at("\\S").size() != new_s.size()) { cell->connections.at("\\A") = new_a; cell->connections.at("\\B") = new_b; cell->connections.at("\\S") = new_s; - if (new_s.__width > 1) { + if (new_s.size() > 1) { cell->type = "$pmux"; - cell->parameters["\\S_WIDTH"] = new_s.__width; + cell->parameters["\\S_WIDTH"] = new_s.size(); } else { cell->type = "$mux"; cell->parameters.erase("\\S_WIDTH"); @@ -700,9 +700,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo assign_map.apply(a); \ if (a.is_fully_const()) { \ a.optimize(); \ - if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \ + if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ - RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, dummy_arg, \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, dummy_arg, \ cell->parameters["\\A_SIGNED"].as_bool(), false, \ cell->parameters["\\Y_WIDTH"].as_int())); \ replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \ @@ -716,9 +716,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ a.optimize(), b.optimize(); \ - if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \ - if (b.__chunks.empty()) b.__chunks.push_back(RTLIL::SigChunk()); \ - RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, b.__chunks[0].data, \ + if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \ + if (b.chunks().empty()) b.chunks().push_back(RTLIL::SigChunk()); \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, b.chunks()[0].data, \ cell->parameters["\\A_SIGNED"].as_bool(), \ cell->parameters["\\B_SIGNED"].as_bool(), \ cell->parameters["\\Y_WIDTH"].as_int())); \ @@ -787,10 +787,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]); RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]); - if (sig_b.is_fully_const() && sig_b.__width <= 32) + if (sig_b.is_fully_const() && sig_b.size() <= 32) std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true; - if (sig_a.is_fully_def() && sig_a.__width <= 32) + if (sig_a.is_fully_def() && sig_a.size() <= 32) { int a_val = sig_a.as_int(); @@ -799,7 +799,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n", cell->name.c_str(), module->name.c_str()); - module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); + module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); module->remove(cell); OPT_DID_SOMETHING = true; @@ -807,7 +807,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - for (int i = 1; i < (a_signed ? sig_a.__width-1 : sig_a.__width); i++) + for (int i = 1; i < (a_signed ? sig_a.size()-1 : sig_a.size()); i++) if (a_val == (1 << i)) { log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n", diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index e844a420..61147f67 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -92,8 +92,8 @@ struct OptMuxtreeWorker muxinfo_t muxinfo; muxinfo.cell = cell; - for (int i = 0; i < sig_s.__width; i++) { - RTLIL::SigSpec sig = sig_b.extract(i*sig_a.__width, sig_a.__width); + for (int i = 0; i < sig_s.size(); i++) { + RTLIL::SigSpec sig = sig_b.extract(i*sig_a.size(), sig_a.size()); RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1)); portinfo_t portinfo; for (int idx : sig2bits(sig)) { @@ -201,7 +201,7 @@ struct OptMuxtreeWorker if (live_ports.size() == 1) { - RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.__width, sig_a.__width); + RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size()); module->connections.push_back(RTLIL::SigSig(sig_y, sig_in)); module->cells.erase(mi.cell->name); delete mi.cell; @@ -211,7 +211,7 @@ struct OptMuxtreeWorker RTLIL::SigSpec new_sig_a, new_sig_b, new_sig_s; for (size_t i = 0; i < live_ports.size(); i++) { - RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.__width, sig_a.__width); + RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.size(), sig_a.size()); if (i == live_ports.size()-1) { new_sig_a = sig_in; } else { @@ -223,11 +223,11 @@ struct OptMuxtreeWorker mi.cell->connections["\\A"] = new_sig_a; mi.cell->connections["\\B"] = new_sig_b; mi.cell->connections["\\S"] = new_sig_s; - if (new_sig_s.__width == 1) { + if (new_sig_s.size() == 1) { mi.cell->type = "$mux"; mi.cell->parameters.erase("\\S_WIDTH"); } else { - mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width); + mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size()); } } } @@ -260,7 +260,7 @@ struct OptMuxtreeWorker std::vector<int> results; assign_map.apply(sig); sig.expand(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire != NULL) { bitDef_t bit(c.wire, c.offset); if (bit2num.count(bit) == 0) { diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 4f1176d9..7ab7233c 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -48,7 +48,7 @@ struct OptReduceWorker sig_a.expand(); RTLIL::SigSpec new_sig_a; - for (auto &chunk : sig_a.__chunks) + for (auto &chunk : sig_a.chunks()) { if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) { if (cell->type == "$reduce_and") { @@ -85,7 +85,7 @@ struct OptReduceWorker } new_sig_a.sort_and_unify(); - if (new_sig_a != sig_a || sig_a.__width != cell->connections["\\A"].__width) { + if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; OPT_DID_SOMETHING = true; @@ -93,7 +93,7 @@ struct OptReduceWorker } cell->connections["\\A"] = new_sig_a; - cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size()); return; } @@ -107,20 +107,20 @@ struct OptReduceWorker std::set<RTLIL::SigSpec> handled_sig; handled_sig.insert(sig_a); - for (int i = 0; i < sig_s.__width; i++) + for (int i = 0; i < sig_s.size(); i++) { - RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.__width, sig_a.__width); + RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.size(), sig_a.size()); if (handled_sig.count(this_b) > 0) continue; RTLIL::SigSpec this_s = sig_s.extract(i, 1); - for (int j = i+1; j < sig_s.__width; j++) { - RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.__width, sig_a.__width); + for (int j = i+1; j < sig_s.size(); j++) { + RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.size(), sig_a.size()); if (this_b == that_b) this_s.append(sig_s.extract(j, 1)); } - if (this_s.__width > 1) + if (this_s.size() > 1) { RTLIL::Wire *reduce_or_wire = new RTLIL::Wire; reduce_or_wire->name = NEW_ID; @@ -131,7 +131,7 @@ struct OptReduceWorker reduce_or_cell->type = "$reduce_or"; reduce_or_cell->connections["\\A"] = this_s; reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.__width); + reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->cells[reduce_or_cell->name] = reduce_or_cell; @@ -144,14 +144,14 @@ struct OptReduceWorker handled_sig.insert(this_b); } - if (new_sig_s.__width != sig_s.__width) { + if (new_sig_s.size() != sig_s.size()) { log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); did_something = true; OPT_DID_SOMETHING = true; total_count++; } - if (new_sig_s.__width == 0) + if (new_sig_s.size() == 0) { module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"])); assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]); @@ -162,8 +162,8 @@ struct OptReduceWorker { cell->connections["\\B"] = new_sig_b; cell->connections["\\S"] = new_sig_s; - if (new_sig_s.__width > 1) { - cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width); + if (new_sig_s.size() > 1) { + cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size()); } else { cell->type = "$mux"; cell->parameters.erase("\\S_WIDTH"); @@ -224,7 +224,7 @@ struct OptReduceWorker cell->connections["\\A"].append(in_tuple.at(0)); cell->connections["\\B"] = RTLIL::SigSpec(); - for (int i = 1; i <= cell->connections["\\S"].__width; i++) + for (int i = 1; i <= cell->connections["\\S"].size(); i++) for (auto &in_tuple : consolidated_in_tuples) cell->connections["\\B"].append(in_tuple.at(i)); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 879f7ddc..4215a7b5 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -100,7 +100,7 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) } } - if (sig_c.is_fully_const() && (!sig_r.__width || !has_init)) { + if (sig_c.is_fully_const() && (!sig_r.size() || !has_init)) { if (val_rv.bits.size() == 0) val_rv = val_init; RTLIL::SigSig conn(sig_q, val_rv); @@ -108,26 +108,26 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) goto delete_dff; } - if (sig_d.is_fully_undef() && sig_r.__width && !has_init) { + if (sig_d.is_fully_undef() && sig_r.size() && !has_init) { RTLIL::SigSig conn(sig_q, val_rv); mod->connections.push_back(conn); goto delete_dff; } - if (sig_d.is_fully_undef() && !sig_r.__width && has_init) { + if (sig_d.is_fully_undef() && !sig_r.size() && has_init) { RTLIL::SigSig conn(sig_q, val_init); mod->connections.push_back(conn); goto delete_dff; } - if (sig_d.is_fully_const() && !sig_r.__width && !has_init) { + if (sig_d.is_fully_const() && !sig_r.size() && !has_init) { RTLIL::SigSig conn(sig_q, sig_d); mod->connections.push_back(conn); goto delete_dff; } - if (sig_d == sig_q && !(sig_r.__width && has_init)) { - if (sig_r.__width) { + if (sig_d == sig_q && !(sig_r.size() && has_init)) { + if (sig_r.size()) { RTLIL::SigSig conn(sig_q, val_rv); mod->connections.push_back(conn); } @@ -182,7 +182,7 @@ struct OptRmdffPass : public Pass { std::vector<std::string> dff_list; for (auto &it : mod_it.second->cells) { if (it.second->type == "$mux" || it.second->type == "$pmux") { - if (it.second->connections.at("\\A").__width == it.second->connections.at("\\B").__width) + if (it.second->connections.at("\\A").size() == it.second->connections.at("\\B").size()) mux_drivers.insert(assign_map(it.second->connections.at("\\Y")), it.second); continue; } diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 07e512cb..819a0e46 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -97,7 +97,7 @@ struct OptShareWorker RTLIL::SigSpec sig = it.second; assign_map.apply(sig); hash_string += "C " + it.first + "="; - for (auto &chunk : sig.__chunks) { + for (auto &chunk : sig.chunks()) { if (chunk.wire) hash_string += "{" + chunk.wire->name + " " + int_to_hash_string(chunk.offset) + " " + diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index a773e5e7..b5763508 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -28,7 +28,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity) { - if (signal.__width != 1) + if (signal.size() != 1) return false; if (signal == ref) return true; @@ -80,13 +80,13 @@ static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::S { for (auto &action : cs->actions) { if (unknown) - rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.__width), &rval); + rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.size()), &rval); else rspec.replace(action.first, action.second, &rval); } for (auto sw : cs->switches) { - if (sw->signal.__width == 0) { + if (sw->signal.size() == 0) { for (auto cs2 : sw->cases) apply_const(mod, rspec, rval, cs2, const_sig, polarity, unknown); } @@ -164,11 +164,11 @@ restart_proc_arst: } for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; - RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.__width); + RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); rspec.expand(), rval.expand(); - for (int i = 0; i < int(rspec.__chunks.size()); i++) - if (rspec.__chunks[i].wire == NULL) - rval.__chunks[i] = rspec.__chunks[i]; + for (int i = 0; i < int(rspec.chunks().size()); i++) + if (rspec.chunks()[i].wire == NULL) + rval.chunks()[i] = rspec.chunks()[i]; rspec.optimize(), rval.optimize(); RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { @@ -252,14 +252,14 @@ struct ProcArstPass : public Pass { if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) for (auto &act : sync->actions) { RTLIL::SigSpec arst_sig, arst_val; - for (auto &chunk : act.first.__chunks) + for (auto &chunk : act.first.chunks()) if (chunk.wire && chunk.wire->attributes.count("\\init")) { RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); value.extend(chunk.wire->width, false); arst_sig.append(chunk); arst_val.append(value.extract(chunk.offset, chunk.width)); } - if (arst_sig.__width) { + if (arst_sig.size()) { log("Added global reset to process %s: %s <- %s\n", proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val)); arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 76866068..682515c5 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -27,7 +27,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth) { - if (sw->signal.__width > 0 && sw->signal.is_fully_const()) + if (sw->signal.size() > 0 && sw->signal.is_fully_const()) { int found_matching_case_idx = -1; for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++) @@ -59,7 +59,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did sw->signal = RTLIL::SigSpec(); } - if (sw->cases.size() == 1 && (sw->signal.__width == 0 || sw->cases[0]->compare.empty())) + if (sw->cases.size() == 1 && (sw->signal.size() == 0 || sw->cases[0]->compare.empty())) { did_something = true; for (auto &action : sw->cases[0]->actions) @@ -91,7 +91,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth) { for (size_t i = 0; i < cs->actions.size(); i++) { - if (cs->actions[i].first.__width == 0) { + if (cs->actions[i].first.size() == 0) { did_something = true; cs->actions.erase(cs->actions.begin() + (i--)); } @@ -114,7 +114,7 @@ static void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_coun bool did_something = true; for (size_t i = 0; i < proc->syncs.size(); i++) { for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++) - if (proc->syncs[i]->actions[j].first.__width == 0) + if (proc->syncs[i]->actions[j].first.size() == 0) proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--)); if (proc->syncs[i]->actions.size() == 0) { delete proc->syncs[i]; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index d3dff8ef..8e5fbe8f 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -32,7 +32,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) for (auto sync : proc->syncs) for (auto &action : sync->actions) - if (action.first.__width > 0) { + if (action.first.size() > 0) { lvalue = action.first; lvalue.sort_and_unify(); break; @@ -44,7 +44,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) this_lvalue.append(action.first); this_lvalue.sort_and_unify(); RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue); - if (common_sig.__width > 0) + if (common_sig.size() > 0) lvalue = common_sig; } @@ -54,8 +54,8 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity, std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc) { - RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.__width); - RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.__width); + RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size()); + RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size()); for (auto &it : async_rules) { @@ -72,24 +72,24 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S else log_abort(); - if (sync_low_signals.__width > 1) { + if (sync_low_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); mod->add(cell); } - if (sync_low_signals.__width > 0) { + if (sync_low_signals.size() > 0) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$not"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = mod->addWire(NEW_ID); @@ -97,12 +97,12 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mod->add(cell); } - if (sync_high_signals.__width > 1) { + if (sync_high_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); @@ -113,30 +113,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S inv_cell->name = NEW_ID; inv_cell->type = "$not"; inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.__width); - inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.__width); + inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); + inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.__width); + inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); mod->add(inv_cell); RTLIL::Cell *mux_set_cell = new RTLIL::Cell; mux_set_cell->name = NEW_ID; mux_set_cell->type = "$mux"; - mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.__width); + mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); mod->add(mux_set_cell); RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; mux_clr_cell->name = NEW_ID; mux_clr_cell->type = "$mux"; - mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.__width); + mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); mod->add(mux_clr_cell); } @@ -147,7 +147,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -168,16 +168,16 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.__width); - RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.__width); - RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.__width); + RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size()); + RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); + RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size()); RTLIL::Cell *inv_set = new RTLIL::Cell; inv_set->name = NEW_ID; inv_set->type = "$not"; inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.__width); - inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.__width); + inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); + inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->connections["\\A"] = sig_set; inv_set->connections["\\Y"] = sig_set_inv; mod->add(inv_set); @@ -185,8 +185,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_set = new RTLIL::Cell; mux_sr_set->name = NEW_ID; mux_sr_set->type = "$mux"; - mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); - mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); + mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); + mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; mux_sr_set->connections["\\Y"] = sig_sr_set; mux_sr_set->connections["\\S"] = set; @@ -195,8 +195,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_clr = new RTLIL::Cell; mux_sr_clr->name = NEW_ID; mux_sr_clr->type = "$mux"; - mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); - mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); + mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); + mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; mux_sr_clr->connections["\\Y"] = sig_sr_clr; mux_sr_clr->connections["\\S"] = set; @@ -206,7 +206,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -233,7 +233,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ cell->attributes = proc->attributes; mod->cells[cell->name] = cell; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); if (arst) { cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1); cell->parameters["\\ARST_VALUE"] = val_rst; @@ -259,14 +259,14 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) RTLIL::SigSpec sig = find_any_lvalue(proc); bool free_sync_level = false; - if (sig.__width == 0) + if (sig.size() == 0) break; log("Creating register for signal `%s.%s' using process `%s.%s'.\n", mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str()); - RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); - RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); + RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); RTLIL::SyncRule *sync_level = NULL; RTLIL::SyncRule *sync_edge = NULL; RTLIL::SyncRule *sync_always = NULL; @@ -276,16 +276,16 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) for (auto sync : proc->syncs) for (auto &action : sync->actions) { - if (action.first.extract(sig).__width == 0) + if (action.first.extract(sig).size() == 0) continue; if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) { if (sync_level != NULL && sync_level != sync) { // log_error("Multiple level sensitive events found for this signal!\n"); many_async_rules[rstval].insert(sync_level); - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); } - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sig.replace(action.first, action.second, &rstval); sync_level = sync; } @@ -324,15 +324,15 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } - assert(inputs.__width == compare.__width); + assert(inputs.size() == compare.size()); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$ne"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.__width); - cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); + cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = inputs; cell->connections["\\B"] = compare; @@ -343,7 +343,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } else { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } } @@ -357,7 +357,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sig.optimize(); if (rstval == sig) { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } @@ -386,7 +386,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.__chunks[0].data, sig, + gen_dff(mod, insig, rstval.chunks()[0].data, sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 0ef17b22..ba1fb5ab 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -60,13 +60,13 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.__chunks.size(); i++) { - if (lhs.__chunks[i].wire == NULL) + for (size_t i = 0; i < lhs.chunks().size(); i++) { + if (lhs.chunks()[i].wire == NULL) continue; - RTLIL::Wire *wire = lhs.__chunks[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.__chunks[i].width); - if (value.__width != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.__chunks[i]), log_signal(value)); + RTLIL::Wire *wire = lhs.chunks()[i].wire; + RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width); + if (value.size() != wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value)); log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); wire->attributes["\\init"] = value.as_const(); offset += wire->width; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2e24e786..cd459d94 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -28,14 +28,14 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs) { for (auto &action : cs->actions) { - if (action.first.__width) + if (action.first.size()) return action.first; } for (auto sw : cs->switches) for (auto cs2 : sw->cases) { RTLIL::SigSpec sig = find_any_lvalue(cs2); - if (sig.__width) + if (sig.size()) return sig; } @@ -46,7 +46,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig) { for (auto &action : cs->actions) { RTLIL::SigSpec lvalue = action.first.extract(sig); - if (lvalue.__width) + if (lvalue.size()) sig = lvalue; } @@ -72,18 +72,18 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, comp.expand(); // get rid of don't-care bits - assert(sig.__width == comp.__width); - for (int i = 0; i < comp.__width; i++) - if (comp.__chunks[i].wire == NULL && comp.__chunks[i].data.bits[0] == RTLIL::State::Sa) { + assert(sig.size() == comp.size()); + for (int i = 0; i < comp.size(); i++) + if (comp.chunks()[i].wire == NULL && comp.chunks()[i].data.bits[0] == RTLIL::State::Sa) { sig.remove(i, 1); comp.remove(i--, 1); } - if (comp.__width == 0) + if (comp.size() == 0) return RTLIL::SigSpec(); sig.optimize(); comp.optimize(); - if (sig.__width == 1 && comp == RTLIL::SigSpec(1,1)) + if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig)); } @@ -101,8 +101,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.__width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.__width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size()); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); eq_cell->connections["\\A"] = sig; @@ -143,7 +143,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw) { - assert(when_signal.__width == else_signal.__width); + assert(when_signal.size() == else_signal.size()); std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); @@ -154,14 +154,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, // compare results RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - if (ctrl_sig.__width == 0) + if (ctrl_sig.size() == 0) return when_signal; - assert(ctrl_sig.__width == 1); + assert(ctrl_sig.size() == 1); // prepare multiplexer output signal RTLIL::Wire *result_wire = new RTLIL::Wire; result_wire->name = sstr.str() + "_Y"; - result_wire->width = when_signal.__width; + result_wire->width = when_signal.size(); mod->wires[result_wire->name] = result_wire; // create the multiplexer itself @@ -171,7 +171,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mod->cells[mux_cell->name] = mux_cell; - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.__width); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); mux_cell->connections["\\A"] = else_signal; mux_cell->connections["\\B"] = when_signal; mux_cell->connections["\\S"] = ctrl_sig; @@ -184,14 +184,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.__width == last_mux_cell->connections["\\A"].__width); + assert(when_signal.size() == last_mux_cell->connections["\\A"].size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - assert(ctrl_sig.__width == 1); + assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; last_mux_cell->connections["\\S"].append(ctrl_sig); last_mux_cell->connections["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].__width; + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -208,7 +208,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs // detect groups of parallel cases std::vector<int> pgroups(sw->cases.size()); if (!sw->get_bool_attribute("\\parallel_case")) { - BitPatternPool pool(sw->signal.__width); + BitPatternPool pool(sw->signal.size()); bool extra_group_for_next_case = false; for (size_t i = 0; i < sw->cases.size(); i++) { RTLIL::CaseRule *cs2 = sw->cases[i]; @@ -224,7 +224,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs if (cs2->compare.empty()) pgroups[i] = pgroups[i-1]+1; if (pgroups[i] != pgroups[i-1]) - pool = BitPatternPool(sw->signal.__width); + pool = BitPatternPool(sw->signal.size()); } for (auto pat : cs2->compare) if (!pat.is_fully_const()) @@ -258,7 +258,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) { RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case); - if (sig.__width == 0) + if (sig.size() == 0) break; if (first) { @@ -270,7 +270,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); - RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.__width)); + RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size())); mod->connections.push_back(RTLIL::SigSig(sig, value)); } } diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 5369617b..03a86246 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -44,7 +44,7 @@ struct BruteForceEquivChecker void run_checker(RTLIL::SigSpec &inputs) { - if (inputs.__width < mod1_inputs.__width) { + if (inputs.size() < mod1_inputs.size()) { RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs; inputs0.append(RTLIL::Const(0, 1)); inputs1.append(RTLIL::Const(1, 1)); @@ -71,9 +71,9 @@ struct BruteForceEquivChecker if (ignore_x_mod1) { sig1.expand(), sig2.expand(); - for (size_t i = 0; i < sig1.__chunks.size(); i++) - if (sig1.__chunks.at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) - sig2.__chunks.at(i) = RTLIL::SigChunk(RTLIL::State::Sx); + for (size_t i = 0; i < sig1.chunks().size(); i++) + if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) + sig2.chunks().at(i) = RTLIL::SigChunk(RTLIL::State::Sx); sig1.optimize(), sig2.optimize(); } @@ -172,11 +172,11 @@ struct VlogHammerReporter log_error("Failed to find solution to SAT problem.\n"); expected_y.expand(); - for (int i = 0; i < expected_y.__width; i++) { + for (int i = 0; i < expected_y.size(); i++) { RTLIL::State solution_bit = y_values.at(i) ? RTLIL::State::S1 : RTLIL::State::S0; - RTLIL::State expected_bit = expected_y.__chunks.at(i).data.bits.at(0); + RTLIL::State expected_bit = expected_y.chunks().at(i).data.bits.at(0); if (model_undef) { - if (y_values.at(expected_y.__width+i)) + if (y_values.at(expected_y.size()+i)) solution_bit = RTLIL::State::Sx; } else { if (expected_bit == RTLIL::State::Sx) @@ -184,17 +184,17 @@ struct VlogHammerReporter } if (solution_bit != expected_bit) { std::string sat_bits, rtl_bits; - for (int k = expected_y.__width-1; k >= 0; k--) { - if (model_undef && y_values.at(expected_y.__width+k)) + for (int k = expected_y.size()-1; k >= 0; k--) { + if (model_undef && y_values.at(expected_y.size()+k)) sat_bits += "x"; else sat_bits += y_values.at(k) ? "1" : "0"; - rtl_bits += expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" : - expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0"; + rtl_bits += expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" : + expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0"; } log_error("Found error in SAT model: y[%d] = %s, should be %s:\n SAT: %s\n RTL: %s\n %*s^\n", int(i), log_signal(solution_bit), log_signal(expected_bit), - sat_bits.c_str(), rtl_bits.c_str(), expected_y.__width-i-1, ""); + sat_bits.c_str(), rtl_bits.c_str(), expected_y.size()-i-1, ""); } } @@ -203,16 +203,16 @@ struct VlogHammerReporter std::vector<int> cmp_vars; std::vector<bool> cmp_vals; - std::vector<bool> y_undef(y_values.begin() + expected_y.__width, y_values.end()); + std::vector<bool> y_undef(y_values.begin() + expected_y.size(), y_values.end()); - for (int i = 0; i < expected_y.__width; i++) + for (int i = 0; i < expected_y.size(); i++) if (y_undef.at(i)) { log(" Toggling undef bit %d to test undef gating.\n", i); if (!ez.solve(y_vec, y_values, ez.IFF(y_vec.at(i), y_values.at(i) ? ez.FALSE : ez.TRUE))) log_error("Failed to find solution with toggled bit!\n"); - cmp_vars.push_back(y_vec.at(expected_y.__width + i)); + cmp_vars.push_back(y_vec.at(expected_y.size() + i)); cmp_vals.push_back(true); } else @@ -220,7 +220,7 @@ struct VlogHammerReporter cmp_vars.push_back(y_vec.at(i)); cmp_vals.push_back(y_values.at(i)); - cmp_vars.push_back(y_vec.at(expected_y.__width + i)); + cmp_vars.push_back(y_vec.at(expected_y.size() + i)); cmp_vals.push_back(false); } @@ -283,7 +283,7 @@ struct VlogHammerReporter while (!ce.eval(sig, undef)) { // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef)); log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name)); - ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width)); + ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size())); } log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str()); @@ -293,13 +293,13 @@ struct VlogHammerReporter rtl_sig.expand(); sat_check(module, recorded_set_vars, recorded_set_vals, sig, false); sat_check(module, recorded_set_vars, recorded_set_vals, sig, true); - } else if (rtl_sig.__width > 0) { + } else if (rtl_sig.size() > 0) { sig.expand(); - if (rtl_sig.__width != sig.__width) + if (rtl_sig.size() != sig.size()) log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); - for (int i = 0; i < sig.__width; i++) - if (rtl_sig.__chunks.at(i).data.bits.at(0) == RTLIL::State::Sx) - sig.__chunks.at(i).data.bits.at(0) = RTLIL::State::Sx; + for (int i = 0; i < sig.size(); i++) + if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx) + sig.chunks().at(i).data.bits.at(0) = RTLIL::State::Sx; } log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str()); @@ -350,7 +350,7 @@ struct VlogHammerReporter } if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const()) log_error("Failed to parse pattern %s!\n", pattern.c_str()); - if (sig.__width < total_input_width) + if (sig.size() < total_input_width) log_error("Pattern %s is to short!\n", pattern.c_str()); patterns.push_back(sig.as_const()); if (invert_pattern) { @@ -470,9 +470,9 @@ struct EvalPass : public Pass { log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str()); if (!rhs.is_fully_const()) log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str()); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - it.first.c_str(), log_signal(lhs), lhs.__width, it.second.c_str(), log_signal(rhs), rhs.__width); + it.first.c_str(), log_signal(lhs), lhs.size(), it.second.c_str(), log_signal(rhs), rhs.size()); ce.set(lhs, rhs.as_const()); } @@ -493,7 +493,7 @@ struct EvalPass : public Pass { if (set_undef) { while (!ce.eval(value, undef)) { log("Failed to evaluate signal %s: Missing value for %s. -> setting to undef\n", log_signal(signal), log_signal(undef)); - ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width)); + ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size())); undef = RTLIL::SigSpec(); } log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value)); @@ -526,15 +526,15 @@ struct EvalPass : public Pass { } std::vector<std::string> tab_line; - for (auto &c : tabsigs.__chunks) + for (auto &c : tabsigs.chunks()) tab_line.push_back(log_signal(c)); tab_sep_colidx = tab_line.size(); - for (auto &c : signal.__chunks) + for (auto &c : signal.chunks()) tab_line.push_back(log_signal(c)); tab.push_back(tab_line); tab_line.clear(); - RTLIL::Const tabvals(0, tabsigs.__width); + RTLIL::Const tabvals(0, tabsigs.size()); do { ce.push(); @@ -548,19 +548,19 @@ struct EvalPass : public Pass { log_signal(tabsigs), log_signal(tabvals), log_signal(this_undef)); return; } - ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.__width)); + ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.size())); undef.append(this_undef); this_undef = RTLIL::SigSpec(); } int pos = 0; - for (auto &c : tabsigs.__chunks) { + for (auto &c : tabsigs.chunks()) { tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width))); pos += c.width; } pos = 0; - for (auto &c : signal.__chunks) { + for (auto &c : signal.chunks()) { tab_line.push_back(log_signal(value.extract(pos, c.width))); pos += c.width; } @@ -602,7 +602,7 @@ struct EvalPass : public Pass { } log("\n"); - if (undef.__width > 0) { + if (undef.size() > 0) { undef.sort_and_unify(); log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef)); } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 4308e736..c9363f4b 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -649,7 +649,7 @@ struct ExposePass : public Pass { { RTLIL::Wire *w = new RTLIL::Wire; w->name = cell->name + sep + RTLIL::unescape_id(it.first); - w->width = it.second.__width; + w->width = it.second.size(); if (ct.cell_input(cell->type, it.first)) w->port_output = true; if (ct.cell_output(cell->type, it.first)) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 8cc59b29..1e47e7de 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -714,7 +714,7 @@ struct FreduceWorker if (grp[i].inverted) { - if (inv_sig.__width == 0) + if (inv_sig.size() == 0) { inv_sig = module->addWire(NEW_ID); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 1cd794b5..79857c5e 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -253,11 +253,11 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, } } - if (all_conditions.__width != 1) { + if (all_conditions.size() != 1) { RTLIL::Cell *reduce_cell = new RTLIL::Cell; reduce_cell->name = NEW_ID; reduce_cell->type = "$reduce_and"; - reduce_cell->parameters["\\A_WIDTH"] = all_conditions.__width; + reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size(); reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; reduce_cell->connections["\\A"] = all_conditions; @@ -283,8 +283,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL::Cell *not_cell = new RTLIL::Cell; not_cell->name = NEW_ID; not_cell->type = "$not"; - not_cell->parameters["\\A_WIDTH"] = all_conditions.__width; - not_cell->parameters["\\A_WIDTH"] = all_conditions.__width; + not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); + not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; not_cell->connections["\\A"] = all_conditions; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 16144932..24968aa2 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -101,10 +101,10 @@ struct SatHelper RTLIL::SigSpec lhs = sigmap(it.second); RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); - log_assert(lhs.__width == rhs.__width); + log_assert(lhs.size() == rhs.size()); RTLIL::SigSpec removed_bits; - for (int i = 0; i < lhs.__width; i++) { + for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); if (!satgen.initial_state.check_all(bit)) { removed_bits.append(bit); @@ -118,10 +118,10 @@ struct SatHelper rhs.optimize(); removed_bits.optimize(); - if (removed_bits.__width) + if (removed_bits.size()) log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); - if (lhs.__width) { + if (lhs.size()) { log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); big_lhs.append(lhs); @@ -140,9 +140,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -166,17 +166,17 @@ struct SatHelper RTLIL::SigSpec rem = satgen.initial_state.export_all(); rem.remove(big_lhs); big_lhs.append(rem); - big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.__width)); + big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.size())); } if (set_init_zero) { RTLIL::SigSpec rem = satgen.initial_state.export_all(); rem.remove(big_lhs); big_lhs.append(rem); - big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.__width)); + big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.size())); } - if (big_lhs.__width == 0) { + if (big_lhs.size() == 0) { log("No constraints for initial state found.\n\n"); return; } @@ -209,9 +209,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -230,9 +230,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import set-constraint for this timestep: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -358,9 +358,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Proof expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import proof-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -386,9 +386,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Proof-x expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import proof-x-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -413,8 +413,8 @@ struct SatHelper satgen.getAsserts(asserts_a, asserts_en, timestep); asserts_a.expand(); asserts_en.expand(); - for (size_t i = 0; i < asserts_a.__chunks.size(); i++) - log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.__chunks[i]), log_signal(asserts_en.__chunks[i])); + for (size_t i = 0; i < asserts_a.chunks().size(); i++) + log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.chunks()[i]), log_signal(asserts_en.chunks()[i])); prove_bits.push_back(satgen.importAsserts(timestep)); } @@ -543,12 +543,12 @@ struct SatHelper std::vector<int> modelUndefExpressions; - for (auto &c : modelSig.__chunks) + for (auto &c : modelSig.chunks()) if (c.wire != NULL) { ModelBlockInfo info; RTLIL::SigSpec chunksig = c; - info.width = chunksig.__width; + info.width = chunksig.size(); info.description = log_signal(chunksig); for (int timestep = -1; timestep <= max_timestep; timestep++) @@ -573,7 +573,7 @@ struct SatHelper // Add initial state signals as collected by satgen // modelSig = satgen.initial_state.export_all(); - for (auto &c : modelSig.__chunks) + for (auto &c : modelSig.chunks()) if (c.wire != NULL) { ModelBlockInfo info; @@ -581,7 +581,7 @@ struct SatHelper info.timestep = 0; info.offset = modelExpressions.size(); - info.width = chunksig.__width; + info.width = chunksig.size(); info.description = log_signal(chunksig); modelInfo.insert(info); diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 95f35bb3..738b0bd6 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -273,11 +273,11 @@ struct ShareWorker RTLIL::SigSpec a2 = c2->connections.at("\\A"); RTLIL::SigSpec y2 = c2->connections.at("\\Y"); - int a_width = std::max(a1.__width, a2.__width); - int y_width = std::max(y1.__width, y2.__width); + int a_width = std::max(a1.size(), a2.size()); + int y_width = std::max(y1.size(), y2.size()); - if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); - if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1(y, y1.__width); - RTLIL::SigSpec new_y2(y, y2.__width); + RTLIL::SigSpec new_y1(y, y1.size()); + RTLIL::SigSpec new_y2(y, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -367,28 +367,28 @@ struct ShareWorker RTLIL::SigSpec b2 = c2->connections.at("\\B"); RTLIL::SigSpec y2 = c2->connections.at("\\Y"); - int a_width = std::max(a1.__width, a2.__width); - int b_width = std::max(b1.__width, b2.__width); - int y_width = std::max(y1.__width, y2.__width); + int a_width = std::max(a1.size(), a2.size()); + int b_width = std::max(b1.size(), b2.size()); + int y_width = std::max(y1.size(), y2.size()); if (c1->type == "$shr" && a_signed) { a_width = std::max(y_width, a_width); - if (a1.__width < y1.__width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.__width), true)->connections.at("\\Y"); - if (a2.__width < y2.__width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.__width), true)->connections.at("\\Y"); + if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->connections.at("\\Y"); + if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->connections.at("\\Y"); - if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); - if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); } else { - if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); - if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); } - if (b1.__width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); - if (b2.__width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); + if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); + if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1(y, y1.__width); - RTLIL::SigSpec new_y2(y, y2.__width); + RTLIL::SigSpec new_y1(y, y1.size()); + RTLIL::SigSpec new_y2(y, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -575,7 +575,7 @@ struct ShareWorker if (activation_patterns_cache[cell].empty()) { log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell]; - module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.__width))); + module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); cells_to_remove.insert(cell); } @@ -811,10 +811,10 @@ struct ShareWorker int other_cell_select_score = 0; for (auto &p : filtered_cell_activation_patterns) - cell_select_score += p.first.__width; + cell_select_score += p.first.size(); for (auto &p : filtered_other_cell_activation_patterns) - other_cell_select_score += p.first.__width; + other_cell_select_score += p.first.size(); RTLIL::Cell *supercell; if (cell_select_score <= other_cell_select_score) { diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 7e57aa0f..a960f2ba 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -133,8 +133,8 @@ namespace needleSig.expand(); haystackSig.expand(); - for (int i = 0; i < std::min(needleSig.__width, haystackSig.__width); i++) { - RTLIL::Wire *needleWire = needleSig.__chunks.at(i).wire, *haystackWire = haystackSig.__chunks.at(i).wire; + for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { + RTLIL::Wire *needleWire = needleSig.chunks().at(i).wire, *haystackWire = haystackSig.chunks().at(i).wire; if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire) if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr)) return false; @@ -193,7 +193,7 @@ namespace RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); conn_sig.expand(); - for (auto &chunk : conn_sig.__chunks) + for (auto &chunk : conn_sig.chunks()) if (chunk.wire != NULL) sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)]++; } @@ -213,7 +213,7 @@ namespace for (auto &conn : cell->connections) { - graph.createPort(cell->name, conn.first, conn.second.__width); + graph.createPort(cell->name, conn.first, conn.second.size()); if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0) continue; @@ -222,9 +222,9 @@ namespace sigmap.apply(conn_sig); conn_sig.expand(); - for (size_t i = 0; i < conn_sig.__chunks.size(); i++) + for (size_t i = 0; i < conn_sig.chunks().size(); i++) { - auto &chunk = conn_sig.__chunks[i]; + auto &chunk = conn_sig.chunks()[i]; assert(chunk.width == 1); if (chunk.wire == NULL) { @@ -269,7 +269,7 @@ namespace sigmap.apply(conn_sig); conn_sig.expand(); - for (auto &chunk : conn_sig.__chunks) + for (auto &chunk : conn_sig.chunks()) if (sig_bit_ref.count(chunk) != 0) { bit_ref_t &bit_ref = sig_bit_ref[chunk]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); @@ -287,7 +287,7 @@ namespace sigmap.apply(conn_sig); conn_sig.expand(); - for (auto &chunk : conn_sig.__chunks) + for (auto &chunk : conn_sig.chunks()) if (sig_bit_ref.count(chunk) != 0) { bit_ref_t &bit_ref = sig_bit_ref[chunk]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); @@ -334,8 +334,8 @@ namespace RTLIL::SigSpec sig = sigmap(conn.second); if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { sig.expand(); - for (int i = 0; i < sig.__width; i++) - for (auto &port : sig2port.find(sig.__chunks[i])) { + for (int i = 0; i < sig.size(); i++) + for (auto &port : sig2port.find(sig.chunks()[i])) { RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1); cell->connections.at(port.first).replace(port.second, bitsig); } @@ -729,7 +729,7 @@ struct ExtractPass : public Pass { for (auto cell : cells) for (auto &conn : cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.__chunks) + for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) wires.insert(chunk.wire); } @@ -756,7 +756,7 @@ struct ExtractPass : public Pass { newCell->parameters = cell->parameters; for (auto &conn : cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.__chunks) + for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); newCell->connections[conn.first] = sig; diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 22f4c7d1..ac41e47c 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo; void hilomap_worker(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { if (!singleton_mode || last_hi.width == 0) { last_hi = RTLIL::SigChunk(module->addWire(NEW_ID)); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index cef5cc89..1eb5c063 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -42,8 +42,8 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_a.__chunks.at(i); - gate->connections["\\Y"] = sig_y.__chunks.at(i); + gate->connections["\\A"] = sig_a.chunks().at(i); + gate->connections["\\Y"] = sig_y.chunks().at(i); module->add(gate); } } @@ -96,8 +96,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_t.__chunks.at(i); - gate->connections["\\Y"] = sig_y.__chunks.at(i); + gate->connections["\\A"] = sig_t.chunks().at(i); + gate->connections["\\Y"] = sig_y.chunks().at(i); module->add(gate); } @@ -115,9 +115,9 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.__chunks.at(i); - gate->connections["\\B"] = sig_b.__chunks.at(i); - gate->connections["\\Y"] = sig_y.__chunks.at(i); + gate->connections["\\A"] = sig_a.chunks().at(i); + gate->connections["\\B"] = sig_b.chunks().at(i); + gate->connections["\\Y"] = sig_y.chunks().at(i); module->add(gate); } } @@ -129,20 +129,20 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - if (sig_y.__width == 0) + if (sig_y.size() == 0) return; - if (sig_a.__width == 0) { - if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width))); - if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); - if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); - if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width))); - if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); + if (sig_a.size() == 0) { + if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); return; } - if (sig_y.__width > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1))); + if (sig_y.size() > 1) { + module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -156,24 +156,24 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec *last_output = NULL; - while (sig_a.__width > 1) + while (sig_a.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.__width / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2); sig_t.expand(); - for (int i = 0; i < sig_a.__width; i += 2) + for (int i = 0; i < sig_a.size(); i += 2) { - if (i+1 == sig_a.__width) { - sig_t.append(sig_a.__chunks.at(i)); + if (i+1 == sig_a.size()) { + sig_t.append(sig_a.chunks().at(i)); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.__chunks.at(i); - gate->connections["\\B"] = sig_a.__chunks.at(i+1); - gate->connections["\\Y"] = sig_t.__chunks.at(i/2); + gate->connections["\\A"] = sig_a.chunks().at(i); + gate->connections["\\B"] = sig_a.chunks().at(i+1); + gate->connections["\\Y"] = sig_t.chunks().at(i/2); last_output = &gate->connections["\\Y"]; module->add(gate); } @@ -204,31 +204,31 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) { sig.expand(); - while (sig.__width > 1) + while (sig.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.__width / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2); sig_t.expand(); - for (int i = 0; i < sig.__width; i += 2) + for (int i = 0; i < sig.size(); i += 2) { - if (i+1 == sig.__width) { - sig_t.append(sig.__chunks.at(i)); + if (i+1 == sig.size()) { + sig_t.append(sig.chunks().at(i)); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_OR_"; - gate->connections["\\A"] = sig.__chunks.at(i); - gate->connections["\\B"] = sig.__chunks.at(i+1); - gate->connections["\\Y"] = sig_t.__chunks.at(i/2); + gate->connections["\\A"] = sig.chunks().at(i); + gate->connections["\\B"] = sig.chunks().at(i+1); + gate->connections["\\Y"] = sig_t.chunks().at(i/2); module->add(gate); } sig = sig_t; } - if (sig.__width == 0) + if (sig.size() == 0) sig = RTLIL::SigSpec(0, 1); } @@ -239,11 +239,11 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - if (sig_y.__width == 0) + if (sig_y.size() == 0) return; - if (sig_y.__width > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1))); + if (sig_y.size() > 1) { + module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -265,11 +265,11 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - if (sig_y.__width == 0) + if (sig_y.size() == 0) return; - if (sig_y.__width > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1))); + if (sig_y.size() > 1) { + module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -304,10 +304,10 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_MUX_"; - gate->connections["\\A"] = sig_a.__chunks.at(i); - gate->connections["\\B"] = sig_b.__chunks.at(i); + gate->connections["\\A"] = sig_a.chunks().at(i); + gate->connections["\\B"] = sig_b.chunks().at(i); gate->connections["\\S"] = cell->connections.at("\\S"); - gate->connections["\\Y"] = sig_y.__chunks.at(i); + gate->connections["\\Y"] = sig_y.chunks().at(i); module->add(gate); } } @@ -317,7 +317,7 @@ static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) int offset = cell->parameters.at("\\OFFSET").as_int(); RTLIL::SigSpec sig_a = cell->connections.at("\\A"); RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.__width))); + module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); } static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) @@ -349,9 +349,9 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\S"] = sig_s.__chunks.at(i); - gate->connections["\\R"] = sig_r.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\S"] = sig_s.chunks().at(i); + gate->connections["\\R"] = sig_r.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } @@ -376,8 +376,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\D"] = sig_d.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\D"] = sig_d.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } @@ -410,10 +410,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\S"] = sig_s.__chunks.at(i); - gate->connections["\\R"] = sig_r.__chunks.at(i); - gate->connections["\\D"] = sig_d.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\S"] = sig_s.chunks().at(i); + gate->connections["\\R"] = sig_r.chunks().at(i); + gate->connections["\\D"] = sig_d.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } @@ -446,8 +446,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0; gate->connections["\\C"] = sig_clk; gate->connections["\\R"] = sig_rst; - gate->connections["\\D"] = sig_d.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\D"] = sig_d.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } @@ -472,8 +472,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\E"] = sig_en; - gate->connections["\\D"] = sig_d.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\D"] = sig_d.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index f7d5efa0..d3e7e20f 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -41,13 +41,13 @@ static void apply_prefix(std::string prefix, std::string &id) static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) { - for (size_t i = 0; i < sig.__chunks.size(); i++) { - if (sig.__chunks[i].wire == NULL) + for (size_t i = 0; i < sig.chunks().size(); i++) { + if (sig.chunks()[i].wire == NULL) continue; - std::string wire_name = sig.__chunks[i].wire->name; + std::string wire_name = sig.chunks()[i].wire->name; apply_prefix(prefix, wire_name); assert(module->wires.count(wire_name) > 0); - sig.__chunks[i].wire = module->wires[wire_name]; + sig.chunks()[i].wire = module->wires[wire_name]; } } @@ -163,11 +163,11 @@ struct TechmapWorker c.second = it.second; apply_prefix(cell->name, c.first, module); } - if (c.second.__width > c.first.__width) - c.second.remove(c.first.__width, c.second.__width - c.first.__width); - if (c.second.__width < c.first.__width) - c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.__width - c.second.__width)); - assert(c.first.__width == c.second.__width); + if (c.second.size() > c.first.size()) + c.second.remove(c.first.size(), c.second.size() - c.first.size()); + if (c.second.size() < c.first.size()) + c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size())); + assert(c.first.size() == c.second.size()); if (flatten_mode) { // more conservative approach: // connect internal and external wires |