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-rw-r--r--techlibs/common/techmap.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index e4974789..44467203 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -19,7 +19,7 @@
*
* The internal logic cell technology mapper.
*
- * This verilog library contains the mapping of internal cells (e.g. $not with
+ * This Verilog library contains the mapping of internal cells (e.g. $not with
* variable bit width) to the internal logic cells (such as the single bit $_NOT_
* gate). Usually this logic network is then mapped to the actual technology
* using e.g. the "abc" pass.