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-rw-r--r--techlibs/ecp5/.gitignore9
-rw-r--r--techlibs/ecp5/Makefile.inc38
-rw-r--r--techlibs/ecp5/arith_map.v2
-rw-r--r--techlibs/ecp5/bram.txt29
-rwxr-xr-xtechlibs/ecp5/brams_connect.py46
-rwxr-xr-xtechlibs/ecp5/brams_init.py22
-rw-r--r--techlibs/ecp5/brams_map.v115
-rw-r--r--techlibs/ecp5/cells_bb.v666
-rw-r--r--techlibs/ecp5/cells_map.v35
-rw-r--r--techlibs/ecp5/cells_sim.v154
-rw-r--r--techlibs/ecp5/dram.txt1
-rw-r--r--techlibs/ecp5/ecp5_ffinit.cc203
-rw-r--r--techlibs/ecp5/latches_map.v11
-rw-r--r--techlibs/ecp5/synth_ecp5.cc19
14 files changed, 1305 insertions, 45 deletions
diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore
new file mode 100644
index 00000000..54c32973
--- /dev/null
+++ b/techlibs/ecp5/.gitignore
@@ -0,0 +1,9 @@
+bram_init_1_2_4.vh
+bram_init_9_18_36.vh
+brams_init.mk
+bram_conn_1.vh
+bram_conn_2.vh
+bram_conn_4.vh
+bram_conn_9.vh
+bram_conn_18.vh
+brams_connect.mk
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 9d324734..4db087e8 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -1,8 +1,44 @@
-OBJS += techlibs/ecp5/synth_ecp5.o
+OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
+
+EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
+.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
+
+techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py
+ $(Q) mkdir -p techlibs/ecp5
+ $(P) python3 $<
+ $(Q) touch $@
+
+techlibs/ecp5/brams_connect.mk: techlibs/ecp5/brams_connect.py
+ $(Q) mkdir -p techlibs/ecp5
+ $(P) python3 $<
+ $(Q) touch $@
+
+
+techlibs/ecp5/bram_init_1_2_4.vh: techlibs/ecp5/brams_init.mk
+techlibs/ecp5/bram_init_9_18_36.vh: techlibs/ecp5/brams_init.mk
+
+techlibs/ecp5/bram_conn_1.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_2.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_4.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_9.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_18.vh: techlibs/ecp5/brams_connect.mk
+
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
+
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_1.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 1094c5f8..eb794760 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -33,7 +33,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
output [Y_WIDTH-1:0] CO;
- wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt
new file mode 100644
index 00000000..f223a42b
--- /dev/null
+++ b/techlibs/ecp5/bram.txt
@@ -0,0 +1,29 @@
+bram $__ECP5_DP16KD
+ init 1
+
+ abits 10 @a10d18
+ dbits 18 @a10d18
+ abits 11 @a11d9
+ dbits 9 @a11d9
+ abits 12 @a12d4
+ dbits 4 @a12d4
+ abits 13 @a13d2
+ dbits 2 @a13d2
+ abits 14 @a14d1
+ dbits 1 @a14d1
+
+ groups 2
+ ports 1 1
+ wrmode 1 0
+ enable 2 1 @a10d18
+ enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
+ transp 0 2
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+match $__ECP5_DP16KD
+ min bits 2048
+ min efficiency 5
+ shuffle_enable B
+endmatch
diff --git a/techlibs/ecp5/brams_connect.py b/techlibs/ecp5/brams_connect.py
new file mode 100755
index 00000000..f86dcfcf
--- /dev/null
+++ b/techlibs/ecp5/brams_connect.py
@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+
+def write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits):
+ ada_conn = [".ADA%d(%s)" % (i, ada_bits[i]) for i in range(len(ada_bits))]
+ adb_conn = [".ADB%d(%s)" % (i, adb_bits[i]) for i in range(len(adb_bits))]
+ dia_conn = [".DIA%d(%s)" % (i, dia_bits[i]) for i in range(len(dia_bits))]
+ dob_conn = [".DOB%d(%s)" % (i, dob_bits[i]) for i in range(len(dob_bits))]
+ print(" %s," % ", ".join(ada_conn), file=f)
+ print(" %s," % ", ".join(adb_conn), file=f)
+ print(" %s," % ", ".join(dia_conn), file=f)
+ print(" %s," % ", ".join(dob_conn), file=f)
+
+with open("techlibs/ecp5/bram_conn_1.vh", "w") as f:
+ ada_bits = ["A1ADDR[%d]" % i for i in range(14)]
+ adb_bits = ["B1ADDR[%d]" % i for i in range(14)]
+ dia_bits = ["A1DATA[0]"] + ["1'b0" for i in range(17)]
+ dob_bits = ["B1DATA[0]"]
+ write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_2.vh", "w") as f:
+ ada_bits = ["1'b0"] + ["A1ADDR[%d]" % i for i in range(13)]
+ adb_bits = ["1'b0"] + ["B1ADDR[%d]" % i for i in range(13)]
+ dia_bits = ["A1DATA[%d]" % i for i in range(2)] + ["1'b0" for i in range(16)]
+ dob_bits = ["B1DATA[%d]" % i for i in range(2)]
+ write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_4.vh", "w") as f:
+ ada_bits = ["1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(12)]
+ adb_bits = ["1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(12)]
+ dia_bits = ["A1DATA[%d]" % i for i in range(4)] + ["1'b0" for i in range(14)]
+ dob_bits = ["B1DATA[%d]" % i for i in range(4)]
+ write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_9.vh", "w") as f:
+ ada_bits = ["1'b0", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(11)]
+ adb_bits = ["1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(11)]
+ dia_bits = ["A1DATA[%d]" % i for i in range(9)] + ["1'b0" for i in range(9)]
+ dob_bits = ["B1DATA[%d]" % i for i in range(9)]
+ write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_18.vh", "w") as f:
+ ada_bits = ["A1EN[0]", "A1EN[1]", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(10)]
+ adb_bits = ["1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(10)]
+ dia_bits = ["A1DATA[%d]" % i for i in range(18)]
+ dob_bits = ["B1DATA[%d]" % i for i in range(18)]
+ write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
diff --git a/techlibs/ecp5/brams_init.py b/techlibs/ecp5/brams_init.py
new file mode 100755
index 00000000..96a47bdc
--- /dev/null
+++ b/techlibs/ecp5/brams_init.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+with open("techlibs/ecp5/bram_init_1_2_4.vh", "w") as f:
+ for i in range(0, 0x40):
+ init_snippets = []
+ for j in range(32):
+ init_snippets.append("INIT[%4d*8 +: 8]" % (32 * i + j))
+ init_snippets.append("3'b000" if (j % 2 == 1) else "1'b0")
+ init_snippets = list(reversed(init_snippets))
+ for k in range(8, 64, 8):
+ init_snippets[k] = "\n " + init_snippets[k]
+ print(".INITVAL_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
+
+with open("techlibs/ecp5/bram_init_9_18_36.vh", "w") as f:
+ for i in range(0, 0x40):
+ init_snippets = []
+ for j in range(16):
+ init_snippets.append("INIT[%3d*18 +: 18]" % (16 * i + j))
+ init_snippets.append("2'b00")
+ init_snippets = list(reversed(init_snippets))
+ for k in range(8, 32, 8):
+ init_snippets[k] = "\n " + init_snippets[k]
+ print(".INITVAL_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
new file mode 100644
index 00000000..b2c13686
--- /dev/null
+++ b/techlibs/ecp5/brams_map.v
@@ -0,0 +1,115 @@
+module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+ parameter CFG_ABITS = 10;
+ parameter CFG_DBITS = 18;
+ parameter CFG_ENABLE_A = 2;
+
+ parameter CLKPOL2 = 1;
+ parameter CLKPOL3 = 1;
+ parameter [18431:0] INIT = 18432'bx;
+ parameter TRANSP2 = 0;
+
+ input CLK2;
+ input CLK3;
+
+ input [CFG_ABITS-1:0] A1ADDR;
+ input [CFG_DBITS-1:0] A1DATA;
+ input [CFG_ENABLE_A-1:0] A1EN;
+
+ input [CFG_ABITS-1:0] B1ADDR;
+ output [CFG_DBITS-1:0] B1DATA;
+ input B1EN;
+
+ localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
+ localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";
+
+ localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
+
+ generate if (CFG_DBITS == 1) begin
+ DP16KD #(
+ `include "bram_init_1_2_4.vh"
+ .DATA_WIDTH_A(1),
+ .DATA_WIDTH_B(1),
+ .CLKAMUX(CLKAMUX),
+ .CLKBMUX(CLKBMUX),
+ .WRITEMODE_A(WRITEMODE_A),
+ .WRITEMODE_B("READBEFOREWRITE"),
+ .GSR("DISABLED")
+ ) _TECHMAP_REPLACE_ (
+ `include "bram_conn_1.vh"
+ .CLKA(CLK2), .CLKB(CLK3),
+ .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+ .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+ .RSTA(1'b0), .RSTB(1'b0)
+ );
+ end else if (CFG_DBITS == 2) begin
+ DP16KD #(
+ `include "bram_init_1_2_4.vh"
+ .DATA_WIDTH_A(2),
+ .DATA_WIDTH_B(2),
+ .CLKAMUX(CLKAMUX),
+ .CLKBMUX(CLKBMUX),
+ .WRITEMODE_A(WRITEMODE_A),
+ .WRITEMODE_B("READBEFOREWRITE"),
+ .GSR("DISABLED")
+ ) _TECHMAP_REPLACE_ (
+ `include "bram_conn_2.vh"
+ .CLKA(CLK2), .CLKB(CLK3),
+ .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+ .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+ .RSTA(1'b0), .RSTB(1'b0)
+ );
+ end else if (CFG_DBITS <= 4) begin
+ DP16KD #(
+ `include "bram_init_1_2_4.vh"
+ .DATA_WIDTH_A(4),
+ .DATA_WIDTH_B(4),
+ .CLKAMUX(CLKAMUX),
+ .CLKBMUX(CLKBMUX),
+ .WRITEMODE_A(WRITEMODE_A),
+ .WRITEMODE_B("READBEFOREWRITE"),
+ .GSR("DISABLED")
+ ) _TECHMAP_REPLACE_ (
+ `include "bram_conn_4.vh"
+ .CLKA(CLK2), .CLKB(CLK3),
+ .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+ .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+ .RSTA(1'b0), .RSTB(1'b0)
+ );
+ end else if (CFG_DBITS <= 9) begin
+ DP16KD #(
+ `include "bram_init_9_18_36.vh"
+ .DATA_WIDTH_A(9),
+ .DATA_WIDTH_B(9),
+ .CLKAMUX(CLKAMUX),
+ .CLKBMUX(CLKBMUX),
+ .WRITEMODE_A(WRITEMODE_A),
+ .WRITEMODE_B("READBEFOREWRITE"),
+ .GSR("DISABLED")
+ ) _TECHMAP_REPLACE_ (
+ `include "bram_conn_9.vh"
+ .CLKA(CLK2), .CLKB(CLK3),
+ .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+ .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+ .RSTA(1'b0), .RSTB(1'b0)
+ );
+ end else if (CFG_DBITS <= 18) begin
+ DP16KD #(
+ `include "bram_init_9_18_36.vh"
+ .DATA_WIDTH_A(18),
+ .DATA_WIDTH_B(18),
+ .CLKAMUX(CLKAMUX),
+ .CLKBMUX(CLKBMUX),
+ .WRITEMODE_A(WRITEMODE_A),
+ .WRITEMODE_B("READBEFOREWRITE"),
+ .GSR("DISABLED")
+ ) _TECHMAP_REPLACE_ (
+ `include "bram_conn_18.vh"
+ .CLKA(CLK2), .CLKB(CLK3),
+ .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+ .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+ .RSTA(1'b0), .RSTB(1'b0)
+ );
+ end else begin
+ wire TECHMAP_FAIL = 1'b1;
+ end endgenerate
+endmodule
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
new file mode 100644
index 00000000..223e19b9
--- /dev/null
+++ b/techlibs/ecp5/cells_bb.v
@@ -0,0 +1,666 @@
+// ECP5 Blackbox cells
+// FIXME: Create sim models
+
+(* blackbox *)
+module MULT18X18D(
+ input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,
+ input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17,
+ input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17,
+ input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB,
+ input CLK0, CLK1, CLK2, CLK3,
+ input CE0, CE1, CE2, CE3,
+ input RST0, RST1, RST2, RST3,
+ input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17,
+ input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17,
+ output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17,
+ output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17,
+ output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17,
+ output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17,
+ output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17,
+ output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,
+ output SIGNEDP
+);
+ parameter REG_INPUTA_CLK = "NONE";
+ parameter REG_INPUTA_CE = "CE0";
+ parameter REG_INPUTA_RST = "RST0";
+ parameter REG_INPUTB_CLK = "NONE";
+ parameter REG_INPUTB_CE = "CE0";
+ parameter REG_INPUTB_RST = "RST0";
+ parameter REG_INPUTC_CLK = "NONE";
+ parameter REG_PIPELINE_CLK = "NONE";
+ parameter REG_PIPELINE_CE = "CE0";
+ parameter REG_PIPELINE_RST = "RST0";
+ parameter REG_OUTPUT_CLK = "NONE";
+ parameter [127:0] CLK0_DIV = "ENABLED";
+ parameter [127:0] CLK1_DIV = "ENABLED";
+ parameter [127:0] CLK2_DIV = "ENABLED";
+ parameter [127:0] CLK3_DIV = "ENABLED";
+ parameter [127:0] GSR = "ENABLED";
+ parameter [127:0] SOURCEB_MODE = "B_SHIFT";
+ parameter [127:0] RESETMODE = "SYNC";
+endmodule
+
+(* blackbox *)
+module ALU54B(
+ input CLK0, CLK1, CLK2, CLK3,
+ input CE0, CE1, CE2, CE3,
+ input RST0, RST1, RST2, RST3,
+ input SIGNEDIA, SIGNEDIB, SIGNEDCIN,
+ input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35,
+ input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35,
+ input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53,
+ input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53,
+ input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35,
+ input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35,
+ input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53,
+ input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10,
+ output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53,
+ output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53,
+ output EQZ, EQZM, EQOM, EQPAT, EQPATB,
+ output OVER, UNDER, OVERUNDER,
+ output SIGNEDR
+);
+ parameter REG_INPUTC0_CLK = "NONE";
+ parameter REG_INPUTC1_CLK = "NONE";
+ parameter REG_OPCODEOP0_0_CLK = "NONE";
+ parameter REG_OPCODEOP0_0_CE = "CE0";
+ parameter REG_OPCODEOP0_0_RST = "RST0";
+ parameter REG_OPCODEOP1_0_CLK = "NONE";
+ parameter REG_OPCODEOP0_1_CLK = "NONE";
+ parameter REG_OPCODEOP0_1_CE = "CE0";
+ parameter REG_OPCODEOP0_1_RST = "RST0";
+ parameter REG_OPCODEIN_0_CLK = "NONE";
+ parameter REG_OPCODEIN_0_CE = "CE0";
+ parameter REG_OPCODEIN_0_RST = "RST0";
+ parameter REG_OPCODEIN_1_CLK = "NONE";
+ parameter REG_OPCODEIN_1_CE = "CE0";
+ parameter REG_OPCODEIN_1_RST = "RST0";
+ parameter REG_OUTPUT0_CLK = "NONE";
+ parameter REG_OUTPUT1_CLK = "NONE";
+ parameter REG_FLAG_CLK = "NONE";
+ parameter [127:0] MCPAT_SOURCE = "STATIC";
+ parameter [127:0] MASKPAT_SOURCE = "STATIC";
+ parameter MASK01 = "0x00000000000000";
+ parameter [127:0] CLK0_DIV = "ENABLED";
+ parameter [127:0] CLK1_DIV = "ENABLED";
+ parameter [127:0] CLK2_DIV = "ENABLED";
+ parameter [127:0] CLK3_DIV = "ENABLED";
+ parameter MCPAT = "0x00000000000000";
+ parameter MASKPAT = "0x00000000000000";
+ parameter RNDPAT = "0x00000000000000";
+ parameter [127:0] GSR = "ENABLED";
+ parameter [127:0] RESETMODE = "SYNC";
+ parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
+ parameter LEGACY = "DISABLED";
+endmodule
+
+(* blackbox *)
+module EHXPLLL (
+ input CLKI, CLKFB,
+ input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG,
+ input STDBY, PLLWAKESYNC,
+ input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3,
+ output CLKOP, CLKOS, CLKOS2, CLKOS3,
+ output LOCK, INTLOCK,
+ output REFCLK, CLKINTFB
+);
+ parameter CLKI_DIV = 1;
+ parameter CLKFB_DIV = 1;
+ parameter CLKOP_DIV = 8;
+ parameter CLKOS_DIV = 8;
+ parameter CLKOS2_DIV = 8;
+ parameter CLKOS3_DIV = 8;
+ parameter CLKOP_ENABLE = "ENABLED";
+ parameter CLKOS_ENABLE = "DISABLED";
+ parameter CLKOS2_ENABLE = "DISABLED";
+ parameter CLKOS3_ENABLE = "DISABLED";
+ parameter CLKOP_CPHASE = 0;
+ parameter CLKOS_CPHASE = 0;
+ parameter CLKOS2_CPHASE = 0;
+ parameter CLKOS3_CPHASE = 0;
+ parameter CLKOP_FPHASE = 0;
+ parameter CLKOS_FPHASE = 0;
+ parameter CLKOS2_FPHASE = 0;
+ parameter CLKOS3_FPHASE = 0;
+ parameter FEEDBK_PATH = "CLKOP";
+ parameter CLKOP_TRIM_POL = "RISING";
+ parameter CLKOP_TRIM_DELAY = 0;
+ parameter CLKOS_TRIM_POL = "RISING";
+ parameter CLKOS_TRIM_DELAY = 0;
+ parameter OUTDIVIDER_MUXA = "DIVA";
+ parameter OUTDIVIDER_MUXB = "DIVB";
+ parameter OUTDIVIDER_MUXC = "DIVC";
+ parameter OUTDIVIDER_MUXD = "DIVD";
+ parameter PLL_LOCK_MODE = 0;
+ parameter PLL_LOCK_DELAY = 200;
+ parameter STDBY_ENABLE = "DISABLED";
+ parameter REFIN_RESET = "DISABLED";
+ parameter SYNC_ENABLE = "DISABLED";
+ parameter INT_LOCK_STICKY = "ENABLED";
+ parameter DPHASE_SOURCE = "DISABLED";
+ parameter PLLRST_ENA = "DISABLED";
+ parameter INTFB_WAKE = "DISABLED";
+endmodule
+
+(* blackbox *)
+module DTR(
+ input STARTPULSE,
+ output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0
+);
+endmodule
+
+(* blackbox *)
+module OSCG(
+ output OSC
+);
+parameter DIV = 128;
+endmodule
+
+(* blackbox *) (* keep *)
+module USRMCLK(
+ input USRMCLKI, USRMCLKTS,
+ output USRMCLKO
+);
+endmodule
+
+(* blackbox *) (* keep *)
+module JTAGG(
+ input TCK, TMS, TDI, JTDO2, JTDO1,
+ output TDO, JTDI, JTCK, JRTI2, JRTI1,
+ output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1
+);
+parameter ER1 = "ENABLED";
+parameter ER2 = "ENABLED";
+endmodule
+
+(* blackbox *)
+module DELAYF(
+ input A, LOADN, MOVE, DIRECTION,
+ output Z, CFLAG
+);
+ parameter DEL_MODE = "USER_DEFINED";
+ parameter DEL_VALUE = 0;
+endmodule
+
+(* blackbox *)
+module DELAYG(
+ input A,
+ output Z
+);
+ parameter DEL_MODE = "USER_DEFINED";
+ parameter DEL_VALUE = 0;
+endmodule
+
+(* blackbox *)
+module IDDRX1F(
+ input D, SCLK, RST,
+ output Q0, Q1
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module IDDRX2F(
+ input D, SCLK, ECLK, RST,
+ output Q0, Q1, Q2, Q3
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module IDDR71B(
+ input D, SCLK, ECLK, RST, ALIGNWD,
+ output Q0, Q1, Q2, Q3, Q4, Q5, Q6
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module IDDRX2DQA(
+ input D, DQSR90, ECLK, SCLK, RST,
+ input RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
+ output Q0, Q1, Q2, Q3, QWL
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX1F(
+ input SCLK, RST, D0, D1,
+ output Q
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX2F(
+ input SCLK, ECLK, RST, D0, D1, D2, D3,
+ output Q
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDR71B(
+ input SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6,
+ output Q
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module OSHX2A(
+ input D0, D1, RST, ECLK, SCLK,
+ output Q
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX2DQA(
+ input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270,
+ output Q
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX2DQSB(
+ input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW,
+ output Q
+);
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module TSHX2DQA(
+ input T0, T1, SCLK, ECLK, DQSW270, RST,
+ output Q
+);
+ parameter GSR = "ENABLED";
+ parameter REGSET = "SET";
+endmodule
+
+(* blackbox *)
+module TSHX2DQSA(
+ input T0, T1, SCLK, ECLK, DQSW, RST,
+ output Q
+);
+ parameter GSR = "ENABLED";
+ parameter REGSET = "SET";
+endmodule
+
+(* blackbox *)
+module DQSBUFM(
+ input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
+ input ECLK, SCLK,
+ input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4,
+ input DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0,
+ input RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
+ output DQSR90, DQSW, DQSW270,
+ output RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
+ output DATAVALID, BURSTDET, RDCFLAG, WRCFLAG
+);
+ parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
+ parameter DQS_LI_DEL_VAL = 0;
+ parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
+ parameter DQS_LO_DEL_VAL = 0;
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module DDRDLLA(
+ input CLK, RST, UDDCNTLN, FREEZE,
+ output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0
+);
+ parameter FORCE_MAX_DELAY = "NO";
+ parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module CLKDIVF(
+ input CLKI, RST, ALIGNWD,
+ output CDIVX
+);
+ parameter GSR = "DISABLED";
+ parameter DIV = "2.0";
+endmodule
+
+(* blackbox *)
+module ECLKSYNCB(
+ input ECLKI, STOP,
+ output ECLKO
+);
+endmodule
+
+(* blackbox *)
+module DCCA(
+ input CLKI, CE,
+ output CLKO
+);
+endmodule
+
+(* blackbox *) (* keep *)
+module DCUA(
+ input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN,
+ input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND,
+ input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK,
+ input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3,
+ input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7,
+ input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11,
+ input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15,
+ input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19,
+ input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23,
+ input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX,
+ input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP,
+ input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE,
+ input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST,
+ input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX,
+ input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7,
+ input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX,
+ input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE,
+ input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0,
+ input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE,
+ input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11,
+ output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND,
+ output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK,
+ output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1,
+ output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5,
+ output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9,
+ output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13,
+ output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17,
+ output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21,
+ output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON,
+ output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN,
+ output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED,
+ output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3,
+ output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7,
+ output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19,
+
+ input D_REFCLKI,
+ output D_FFS_PLOL
+);
+ parameter CH0_AUTO_CALIB_EN = "0b0";
+ parameter CH0_AUTO_FACQ_EN = "0b0";
+ parameter CH0_BAND_THRESHOLD = "0b000000";
+ parameter CH0_CALIB_CK_MODE = "0b0";
+ parameter CH0_CC_MATCH_1 = "0b0000000000";
+ parameter CH0_CC_MATCH_2 = "0b0000000000";
+ parameter CH0_CC_MATCH_3 = "0b0000000000";
+ parameter CH0_CC_MATCH_4 = "0b0000000000";
+ parameter CH0_CDR_CNT4SEL = "0b00";
+ parameter CH0_CDR_CNT8SEL = "0b00";
+ parameter CH0_CTC_BYPASS = "0b0";
+ parameter CH0_DCOATDCFG = "0b00";
+ parameter CH0_DCOATDDLY = "0b00";
+ parameter CH0_DCOBYPSATD = "0b0";
+ parameter CH0_DCOCALDIV = "0b000";
+ parameter CH0_DCOCTLGI = "0b000";
+ parameter CH0_DCODISBDAVOID = "0b0";
+ parameter CH0_DCOFLTDAC = "0b00";
+ parameter CH0_DCOFTNRG = "0b000";
+ parameter CH0_DCOIOSTUNE = "0b000";
+ parameter CH0_DCOITUNE = "0b00";
+ parameter CH0_DCOITUNE4LSB = "0b000";
+ parameter CH0_DCOIUPDNX2 = "0b0";
+ parameter CH0_DCONUOFLSB = "0b000";
+ parameter CH0_DCOSCALEI = "0b00";
+ parameter CH0_DCOSTARTVAL = "0b000";
+ parameter CH0_DCOSTEP = "0b00";
+ parameter CH0_DEC_BYPASS = "0b0";
+ parameter CH0_ENABLE_CG_ALIGN = "0b0";
+ parameter CH0_ENC_BYPASS = "0b0";
+ parameter CH0_FF_RX_F_CLK_DIS = "0b0";
+ parameter CH0_FF_RX_H_CLK_EN = "0b0";
+ parameter CH0_FF_TX_F_CLK_DIS = "0b0";
+ parameter CH0_FF_TX_H_CLK_EN = "0b0";
+ parameter CH0_GE_AN_ENABLE = "0b0";
+ parameter CH0_INVERT_RX = "0b0";
+ parameter CH0_INVERT_TX = "0b0";
+ parameter CH0_LDR_CORE2TX_SEL = "0b0";
+ parameter CH0_LDR_RX2CORE_SEL = "0b0";
+ parameter CH0_LEQ_OFFSET_SEL = "0b0";
+ parameter CH0_LEQ_OFFSET_TRIM = "0b000";
+ parameter CH0_LSM_DISABLE = "0b0";
+ parameter CH0_MATCH_2_ENABLE = "0b0";
+ parameter CH0_MATCH_4_ENABLE = "0b0";
+ parameter CH0_MIN_IPG_CNT = "0b00";
+ parameter CH0_PCIE_EI_EN = "0b0";
+ parameter CH0_PCIE_MODE = "0b0";
+ parameter CH0_PCS_DET_TIME_SEL = "0b00";
+ parameter CH0_PDEN_SEL = "0b0";
+ parameter CH0_PRBS_ENABLE = "0b0";
+ parameter CH0_PRBS_LOCK = "0b0";
+ parameter CH0_PRBS_SELECTION = "0b0";
+ parameter CH0_RATE_MODE_RX = "0b0";
+ parameter CH0_RATE_MODE_TX = "0b0";
+ parameter CH0_RCV_DCC_EN = "0b0";
+ parameter CH0_REG_BAND_OFFSET = "0b0000";
+ parameter CH0_REG_BAND_SEL = "0b000000";
+ parameter CH0_REG_IDAC_EN = "0b0";
+ parameter CH0_REG_IDAC_SEL = "0b0000000000";
+ parameter CH0_REQ_EN = "0b0";
+ parameter CH0_REQ_LVL_SET = "0b00";
+ parameter CH0_RIO_MODE = "0b0";
+ parameter CH0_RLOS_SEL = "0b0";
+ parameter CH0_RPWDNB = "0b0";
+ parameter CH0_RTERM_RX = "0b00000";
+ parameter CH0_RTERM_TX = "0b00000";
+ parameter CH0_RXIN_CM = "0b00";
+ parameter CH0_RXTERM_CM = "0b00";
+ parameter CH0_RX_DCO_CK_DIV = "0b000";
+ parameter CH0_RX_DIV11_SEL = "0b0";
+ parameter CH0_RX_GEAR_BYPASS = "0b0";
+ parameter CH0_RX_GEAR_MODE = "0b0";
+ parameter CH0_RX_LOS_CEQ = "0b00";
+ parameter CH0_RX_LOS_EN = "0b0";
+ parameter CH0_RX_LOS_HYST_EN = "0b0";
+ parameter CH0_RX_LOS_LVL = "0b000";
+ parameter CH0_RX_RATE_SEL = "0b0000";
+ parameter CH0_RX_SB_BYPASS = "0b0";
+ parameter CH0_SB_BYPASS = "0b0";
+ parameter CH0_SEL_SD_RX_CLK = "0b0";
+ parameter CH0_TDRV_DAT_SEL = "0b00";
+ parameter CH0_TDRV_POST_EN = "0b0";
+ parameter CH0_TDRV_PRE_EN = "0b0";
+ parameter CH0_TDRV_SLICE0_CUR = "0b000";
+ parameter CH0_TDRV_SLICE0_SEL = "0b00";
+ parameter CH0_TDRV_SLICE1_CUR = "0b000";
+ parameter CH0_TDRV_SLICE1_SEL = "0b00";
+ parameter CH0_TDRV_SLICE2_CUR = "0b00";
+ parameter CH0_TDRV_SLICE2_SEL = "0b00";
+ parameter CH0_TDRV_SLICE3_CUR = "0b00";
+ parameter CH0_TDRV_SLICE3_SEL = "0b00";
+ parameter CH0_TDRV_SLICE4_CUR = "0b00";
+ parameter CH0_TDRV_SLICE4_SEL = "0b00";
+ parameter CH0_TDRV_SLICE5_CUR = "0b00";
+ parameter CH0_TDRV_SLICE5_SEL = "0b00";
+ parameter CH0_TPWDNB = "0b0";
+ parameter CH0_TX_CM_SEL = "0b00";
+ parameter CH0_TX_DIV11_SEL = "0b0";
+ parameter CH0_TX_GEAR_BYPASS = "0b0";
+ parameter CH0_TX_GEAR_MODE = "0b0";
+ parameter CH0_TX_POST_SIGN = "0b0";
+ parameter CH0_TX_PRE_SIGN = "0b0";
+ parameter CH0_UC_MODE = "0b0";
+ parameter CH0_UDF_COMMA_A = "0b0000000000";
+ parameter CH0_UDF_COMMA_B = "0b0000000000";
+ parameter CH0_UDF_COMMA_MASK = "0b0000000000";
+ parameter CH0_WA_BYPASS = "0b0";
+ parameter CH0_WA_MODE = "0b0";
+ parameter CH1_AUTO_CALIB_EN = "0b0";
+ parameter CH1_AUTO_FACQ_EN = "0b0";
+ parameter CH1_BAND_THRESHOLD = "0b000000";
+ parameter CH1_CALIB_CK_MODE = "0b0";
+ parameter CH1_CC_MATCH_1 = "0b0000000000";
+ parameter CH1_CC_MATCH_2 = "0b0000000000";
+ parameter CH1_CC_MATCH_3 = "0b0000000000";
+ parameter CH1_CC_MATCH_4 = "0b0000000000";
+ parameter CH1_CDR_CNT4SEL = "0b00";
+ parameter CH1_CDR_CNT8SEL = "0b00";
+ parameter CH1_CTC_BYPASS = "0b0";
+ parameter CH1_DCOATDCFG = "0b00";
+ parameter CH1_DCOATDDLY = "0b00";
+ parameter CH1_DCOBYPSATD = "0b0";
+ parameter CH1_DCOCALDIV = "0b000";
+ parameter CH1_DCOCTLGI = "0b000";
+ parameter CH1_DCODISBDAVOID = "0b0";
+ parameter CH1_DCOFLTDAC = "0b00";
+ parameter CH1_DCOFTNRG = "0b000";
+ parameter CH1_DCOIOSTUNE = "0b000";
+ parameter CH1_DCOITUNE = "0b00";
+ parameter CH1_DCOITUNE4LSB = "0b000";
+ parameter CH1_DCOIUPDNX2 = "0b0";
+ parameter CH1_DCONUOFLSB = "0b000";
+ parameter CH1_DCOSCALEI = "0b00";
+ parameter CH1_DCOSTARTVAL = "0b000";
+ parameter CH1_DCOSTEP = "0b00";
+ parameter CH1_DEC_BYPASS = "0b0";
+ parameter CH1_ENABLE_CG_ALIGN = "0b0";
+ parameter CH1_ENC_BYPASS = "0b0";
+ parameter CH1_FF_RX_F_CLK_DIS = "0b0";
+ parameter CH1_FF_RX_H_CLK_EN = "0b0";
+ parameter CH1_FF_TX_F_CLK_DIS = "0b0";
+ parameter CH1_FF_TX_H_CLK_EN = "0b0";
+ parameter CH1_GE_AN_ENABLE = "0b0";
+ parameter CH1_INVERT_RX = "0b0";
+ parameter CH1_INVERT_TX = "0b0";
+ parameter CH1_LDR_CORE2TX_SEL = "0b0";
+ parameter CH1_LDR_RX2CORE_SEL = "0b0";
+ parameter CH1_LEQ_OFFSET_SEL = "0b0";
+ parameter CH1_LEQ_OFFSET_TRIM = "0b000";
+ parameter CH1_LSM_DISABLE = "0b0";
+ parameter CH1_MATCH_2_ENABLE = "0b0";
+ parameter CH1_MATCH_4_ENABLE = "0b0";
+ parameter CH1_MIN_IPG_CNT = "0b00";
+ parameter CH1_PCIE_EI_EN = "0b0";
+ parameter CH1_PCIE_MODE = "0b0";
+ parameter CH1_PCS_DET_TIME_SEL = "0b00";
+ parameter CH1_PDEN_SEL = "0b0";
+ parameter CH1_PRBS_ENABLE = "0b0";
+ parameter CH1_PRBS_LOCK = "0b0";
+ parameter CH1_PRBS_SELECTION = "0b0";
+ parameter CH1_RATE_MODE_RX = "0b0";
+ parameter CH1_RATE_MODE_TX = "0b0";
+ parameter CH1_RCV_DCC_EN = "0b0";
+ parameter CH1_REG_BAND_OFFSET = "0b0000";
+ parameter CH1_REG_BAND_SEL = "0b000000";
+ parameter CH1_REG_IDAC_EN = "0b0";
+ parameter CH1_REG_IDAC_SEL = "0b0000000000";
+ parameter CH1_REQ_EN = "0b0";
+ parameter CH1_REQ_LVL_SET = "0b00";
+ parameter CH1_RIO_MODE = "0b0";
+ parameter CH1_RLOS_SEL = "0b0";
+ parameter CH1_RPWDNB = "0b0";
+ parameter CH1_RTERM_RX = "0b00000";
+ parameter CH1_RTERM_TX = "0b00000";
+ parameter CH1_RXIN_CM = "0b00";
+ parameter CH1_RXTERM_CM = "0b00";
+ parameter CH1_RX_DCO_CK_DIV = "0b000";
+ parameter CH1_RX_DIV11_SEL = "0b0";
+ parameter CH1_RX_GEAR_BYPASS = "0b0";
+ parameter CH1_RX_GEAR_MODE = "0b0";
+ parameter CH1_RX_LOS_CEQ = "0b00";
+ parameter CH1_RX_LOS_EN = "0b0";
+ parameter CH1_RX_LOS_HYST_EN = "0b0";
+ parameter CH1_RX_LOS_LVL = "0b000";
+ parameter CH1_RX_RATE_SEL = "0b0000";
+ parameter CH1_RX_SB_BYPASS = "0b0";
+ parameter CH1_SB_BYPASS = "0b0";
+ parameter CH1_SEL_SD_RX_CLK = "0b0";
+ parameter CH1_TDRV_DAT_SEL = "0b00";
+ parameter CH1_TDRV_POST_EN = "0b0";
+ parameter CH1_TDRV_PRE_EN = "0b0";
+ parameter CH1_TDRV_SLICE0_CUR = "0b000";
+ parameter CH1_TDRV_SLICE0_SEL = "0b00";
+ parameter CH1_TDRV_SLICE1_CUR = "0b000";
+ parameter CH1_TDRV_SLICE1_SEL = "0b00";
+ parameter CH1_TDRV_SLICE2_CUR = "0b00";
+ parameter CH1_TDRV_SLICE2_SEL = "0b00";
+ parameter CH1_TDRV_SLICE3_CUR = "0b00";
+ parameter CH1_TDRV_SLICE3_SEL = "0b00";
+ parameter CH1_TDRV_SLICE4_CUR = "0b00";
+ parameter CH1_TDRV_SLICE4_SEL = "0b00";
+ parameter CH1_TDRV_SLICE5_CUR = "0b00";
+ parameter CH1_TDRV_SLICE5_SEL = "0b00";
+ parameter CH1_TPWDNB = "0b0";
+ parameter CH1_TX_CM_SEL = "0b00";
+ parameter CH1_TX_DIV11_SEL = "0b0";
+ parameter CH1_TX_GEAR_BYPASS = "0b0";
+ parameter CH1_TX_GEAR_MODE = "0b0";
+ parameter CH1_TX_POST_SIGN = "0b0";
+ parameter CH1_TX_PRE_SIGN = "0b0";
+ parameter CH1_UC_MODE = "0b0";
+ parameter CH1_UDF_COMMA_A = "0b0000000000";
+ parameter CH1_UDF_COMMA_B = "0b0000000000";
+ parameter CH1_UDF_COMMA_MASK = "0b0000000000";
+ parameter CH1_WA_BYPASS = "0b0";
+ parameter CH1_WA_MODE = "0b0";
+ parameter D_BITCLK_FROM_ND_EN = "0b0";
+ parameter D_BITCLK_LOCAL_EN = "0b0";
+ parameter D_BITCLK_ND_EN = "0b0";
+ parameter D_BUS8BIT_SEL = "0b0";
+ parameter D_CDR_LOL_SET = "0b00";
+ parameter D_CMUSETBIASI = "0b00";
+ parameter D_CMUSETI4CPP = "0b0000";
+ parameter D_CMUSETI4CPZ = "0b0000";
+ parameter D_CMUSETI4VCO = "0b00";
+ parameter D_CMUSETICP4P = "0b00";
+ parameter D_CMUSETICP4Z = "0b000";
+ parameter D_CMUSETINITVCT = "0b00";
+ parameter D_CMUSETISCL4VCO = "0b000";
+ parameter D_CMUSETP1GM = "0b000";
+ parameter D_CMUSETP2AGM = "0b000";
+ parameter D_CMUSETZGM = "0b000";
+ parameter D_DCO_CALIB_TIME_SEL = "0b00";
+ parameter D_HIGH_MARK = "0b0000";
+ parameter D_IB_PWDNB = "0b0";
+ parameter D_ISETLOS = "0b00000000";
+ parameter D_LOW_MARK = "0b0000";
+ parameter D_MACROPDB = "0b0";
+ parameter D_PD_ISET = "0b00";
+ parameter D_PLL_LOL_SET = "0b00";
+ parameter D_REFCK_MODE = "0b000";
+ parameter D_REQ_ISET = "0b000";
+ parameter D_RG_EN = "0b0";
+ parameter D_RG_SET = "0b00";
+ parameter D_SETICONST_AUX = "0b00";
+ parameter D_SETICONST_CH = "0b00";
+ parameter D_SETIRPOLY_AUX = "0b00";
+ parameter D_SETIRPOLY_CH = "0b00";
+ parameter D_SETPLLRC = "0b000000";
+ parameter D_SYNC_LOCAL_EN = "0b0";
+ parameter D_SYNC_ND_EN = "0b0";
+ parameter D_TXPLL_PWDNB = "0b0";
+ parameter D_TX_VCO_CK_DIV = "0b000";
+ parameter D_XGE_MODE = "0b0";
+
+// These parameters don't do anything but are
+// needed for compatibility with Diamond
+ parameter D_TX_MAX_RATE = "2.5";
+ parameter D_RX_MAX_RATE = "2.5";
+ parameter CH0_TXAMPLITUDE = "0d1300";
+ parameter CH1_TXAMPLITUDE = "0d1300";
+ parameter CH0_PROTOCOL = "8B10B";
+ parameter CH1_PROTOCOL = "8B10B";
+ parameter CH0_CDR_MAX_RATE = "2.5";
+ parameter CH1_CDR_MAX_RATE = "2.5";
+endmodule
+
+(* blackbox *)
+module EXTREFB (
+ input REFCLKP, REFCLKN,
+ output REFCLKO
+);
+ parameter REFCK_PWDNB = "0b0";
+ parameter REFCK_RTERM = "0b0";
+ parameter REFCK_DCBIAS_EN = "0b0";
+endmodule
+
+(* blackbox *)
+module PCSCLKDIV (
+ input CLKI, RST, SEL2, SEL1, SEL0,
+ output CDIV1, CDIVX
+);
+ parameter GSR = "DISABLED";
+endmodule
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 48162a4d..6ab4b69f 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -7,46 +7,49 @@ module \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .C
module \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
module \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
module \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
+module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 1700694e..1e4002ee 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 (
input RAD0, RAD1, RAD2, RAD3,
output DO0, DO1
);
- parameter WCKMUX = "WCK";
+ parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter INITVAL_0 = 16'h0000;
parameter INITVAL_1 = 16'h0000;
@@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 (
input [3:0] RAD,
output [3:0] DO
);
- parameter WCKMUX = "WCK";
+ parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
@@ -203,13 +203,14 @@ endmodule
// ---------------------------------------
-module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
+module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter GSR = "ENABLED";
parameter [127:0] CEMUX = "1";
parameter CLKMUX = "CLK";
parameter LSRMUX = "LSR";
parameter SRMODE = "LSR_OVER_CE";
parameter REGSET = "RESET";
+ parameter [127:0] LSRMODE = "LSR";
reg muxce;
always @(*)
@@ -222,8 +223,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
-
- localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+ wire srval;
+ generate
+ if (LSRMODE == "PRLD")
+ assign srval = M;
+ else
+ assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+ endgenerate
initial Q = srval;
@@ -257,7 +263,7 @@ assign O = I;
endmodule
// ---------------------------------------
-
+(* keep *)
module TRELLIS_IO(
inout B,
input I,
@@ -265,16 +271,18 @@ module TRELLIS_IO(
output O
);
parameter DIR = "INPUT";
+ reg T_pd;
+ always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
generate
if (DIR == "INPUT") begin
assign B = 1'bz;
assign O = B;
end else if (DIR == "OUTPUT") begin
- assign B = T ? 1'bz : I;
+ assign B = T_pd ? 1'bz : I;
assign O = 1'bx;
- end else if (DIR == "INOUT") begin
- assign B = T ? 1'bz : I;
+ end else if (DIR == "BIDIR") begin
+ assign B = T_pd ? 1'bz : I;
assign O = B;
end else begin
ERROR_UNKNOWN_IO_MODE error();
@@ -337,6 +345,8 @@ module TRELLIS_SLICE(
parameter REG1_SD = "0";
parameter REG0_REGSET = "RESET";
parameter REG1_REGSET = "RESET";
+ parameter REG0_LSRMODE = "LSR";
+ parameter REG1_LSRMODE = "LSR";
parameter [127:0] CCU2_INJECT1_0 = "NO";
parameter [127:0] CCU2_INJECT1_1 = "NO";
parameter WREMUX = "WRE";
@@ -426,10 +436,11 @@ module TRELLIS_SLICE(
.CLKMUX(CLKMUX),
.LSRMUX(LSRMUX),
.SRMODE(SRMODE),
- .REGSET(REG0_REGSET)
+ .REGSET(REG0_REGSET),
+ .LSRMODE(REG0_LSRMODE)
) ff_0 (
.CLK(CLK), .LSR(LSR), .CE(CE),
- .DI(muxdi0),
+ .DI(muxdi0), .M(M0),
.Q(Q0)
);
TRELLIS_FF #(
@@ -438,11 +449,128 @@ module TRELLIS_SLICE(
.CLKMUX(CLKMUX),
.LSRMUX(LSRMUX),
.SRMODE(SRMODE),
- .REGSET(REG1_REGSET)
+ .REGSET(REG1_REGSET),
+ .LSRMODE(REG1_LSRMODE)
) ff_1 (
.CLK(CLK), .LSR(LSR), .CE(CE),
- .DI(muxdi1),
+ .DI(muxdi1), .M(M1),
.Q(Q1)
);
endmodule
+(* blackbox *)
+module DP16KD(
+ input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
+ input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
+ input CEA, OCEA, CLKA, WEA, RSTA,
+ input CSA2, CSA1, CSA0,
+ output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
+
+ input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
+ input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
+ input CEB, OCEB, CLKB, WEB, RSTB,
+ input CSB2, CSB1, CSB0,
+ output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
+);
+ parameter DATA_WIDTH_A = 18;
+ parameter DATA_WIDTH_B = 18;
+
+ parameter REGMODE_A = "NOREG";
+ parameter REGMODE_B = "NOREG";
+
+ parameter RESETMODE = "SYNC";
+ parameter ASYNC_RESET_RELEASE = "SYNC";
+
+ parameter CSDECODE_A = "0b000";
+ parameter CSDECODE_B = "0b000";
+
+ parameter WRITEMODE_A = "NORMAL";
+ parameter WRITEMODE_B = "NORMAL";
+
+ parameter CLKAMUX = "CLKA";
+ parameter CLKBMUX = "CLKB";
+
+ parameter GSR = "ENABLED";
+
+ parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+endmodule
+
+// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
+module FD1S3BX(input PD, D, CK, output Q);
+ TRELLIS_FF #(
+ .GSR("DISABLED"),
+ .CEMUX("1"),
+ .CLKMUX("CLK"),
+ .LSRMUX("LSR"),
+ .REGSET("SET"),
+ .SRMODE("ASYNC")
+ ) tff_i (
+ .CLK(CK),
+ .LSR(PD),
+ .DI(D),
+ .Q(Q)
+ );
+endmodule
diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt
index b3252fa9..b9435742 100644
--- a/techlibs/ecp5/dram.txt
+++ b/techlibs/ecp5/dram.txt
@@ -13,4 +13,5 @@ endbram
match $__TRELLIS_DPR16X4
make_outreg
+ min wports 1
endmatch
diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc
new file mode 100644
index 00000000..dbd16cac
--- /dev/null
+++ b/techlibs/ecp5/ecp5_ffinit.cc
@@ -0,0 +1,203 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018-19 David Shah <david@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Ecp5FfinitPass : public Pass {
+ Ecp5FfinitPass() : Pass("ecp5_ffinit", "ECP5: handle FF init values") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" ecp5_ffinit [options] [selection]\n");
+ log("\n");
+ log("Remove init values for FF output signals when equal to reset value.\n");
+ log("If reset is not used, set the reset value to the init value, otherwise\n");
+ log("unmap out the reset (if not an async reset).\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing ECP5_FFINIT pass (implement FF init values).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ // if (args[argidx] == "-singleton") {
+ // singleton_mode = true;
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ {
+ log("Handling FF init values in %s.\n", log_id(module));
+
+ SigMap sigmap(module);
+ pool<Wire*> init_wires;
+ dict<SigBit, State> initbits;
+ dict<SigBit, SigBit> initbit_to_wire;
+ pool<SigBit> handled_initbits;
+
+ for (auto wire : module->selected_wires())
+ {
+ if (wire->attributes.count("\\init") == 0)
+ continue;
+
+ SigSpec wirebits = sigmap(wire);
+ Const initval = wire->attributes.at("\\init");
+ init_wires.insert(wire);
+
+ for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
+ {
+ SigBit bit = wirebits[i];
+ State val = initval[i];
+
+ if (val != State::S0 && val != State::S1)
+ continue;
+
+ if (initbits.count(bit)) {
+ if (initbits.at(bit) != val) {
+ log_warning("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
+ log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
+ log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
+ initbits.at(bit) = State::Sx;
+ }
+ continue;
+ }
+
+ initbits[bit] = val;
+ initbit_to_wire[bit] = SigBit(wire, i);
+ }
+ }
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type != "\\TRELLIS_FF")
+ continue;
+ SigSpec sig_d = cell->getPort("\\DI");
+ SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_lsr = cell->getPort("\\LSR");
+
+ if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
+ continue;
+
+ SigBit bit_d = sigmap(sig_d[0]);
+ SigBit bit_q = sigmap(sig_q[0]);
+
+ std::string regset = "RESET";
+ if (cell->hasParam("\\REGSET"))
+ regset = cell->getParam("\\REGSET").decode_string();
+ State resetState;
+ if (regset == "SET")
+ resetState = State::S1;
+ else if (regset == "RESET")
+ resetState = State::S0;
+ else
+ log_error("FF cell %s has illegal REGSET value %s.\n",
+ log_id(cell), regset.c_str());
+
+ if (!initbits.count(bit_q))
+ continue;
+
+ State val = initbits.at(bit_q);
+
+ if (val == State::Sx)
+ continue;
+
+ log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type),
+ log_signal(bit_q), val != State::S0 ? '1' : '0');
+ // Initval is the same as the reset state. Matches hardware, nowt more to do
+ if (val == resetState) {
+ handled_initbits.insert(bit_q);
+ continue;
+ }
+
+ if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) {
+ std::string srmode = "LSR_OVER_CE";
+ if (cell->hasParam("\\SRMODE"))
+ srmode = cell->getParam("\\SRMODE").decode_string();
+ if (srmode == "ASYNC") {
+ log("Async reset value %c for FF cell %s inconsistent with init value %c.\n",
+ resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0');
+ } else {
+ SigBit bit_lsr = sigmap(sig_lsr[0]);
+ Wire *new_bit_d = module->addWire(NEW_ID);
+ if (resetState == State::S0) {
+ module->addAndnotGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
+ } else {
+ module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
+ }
+
+ cell->setPort("\\DI", new_bit_d);
+ cell->setPort("\\LSR", State::S0);
+
+ if(cell->hasPort("\\CE")) {
+ std::string cemux = "CE";
+ if (cell->hasParam("\\CEMUX"))
+ cemux = cell->getParam("\\CEMUX").decode_string();
+ SigSpec sig_ce = cell->getPort("\\CE");
+ if (GetSize(sig_ce) >= 1) {
+ SigBit bit_ce = sigmap(sig_ce[0]);
+ Wire *new_bit_ce = module->addWire(NEW_ID);
+ if (cemux == "INV")
+ module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
+ else
+ module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
+ cell->setPort("\\CE", new_bit_ce);
+ }
+ }
+ cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+ handled_initbits.insert(bit_q);
+ }
+ } else {
+ cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+ handled_initbits.insert(bit_q);
+ }
+ }
+
+ for (auto wire : init_wires)
+ {
+ if (wire->attributes.count("\\init") == 0)
+ continue;
+
+ SigSpec wirebits = sigmap(wire);
+ Const &initval = wire->attributes.at("\\init");
+ bool remove_attribute = true;
+
+ for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
+ if (handled_initbits.count(wirebits[i]))
+ initval[i] = State::Sx;
+ else if (initval[i] != State::Sx)
+ remove_attribute = false;
+ }
+
+ if (remove_attribute)
+ wire->attributes.erase("\\init");
+ }
+ }
+ }
+} Ecp5FfinitPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ecp5/latches_map.v b/techlibs/ecp5/latches_map.v
new file mode 100644
index 00000000..c28f88cf
--- /dev/null
+++ b/techlibs/ecp5/latches_map.v
@@ -0,0 +1,11 @@
+module \$_DLATCH_N_ (E, D, Q);
+ wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+ input E, D;
+ output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+ wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+ input E, D;
+ output Q = E ? D : Q;
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index a13dd8d4..4b889d67 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -189,7 +189,7 @@ struct SynthEcp5Pass : public ScriptPass
extra_args(args, argidx, design);
if (!design->full_selection())
- log_cmd_error("This comannd only operates on fully selected designs!\n");
+ log_cmd_error("This command only operates on fully selected designs!\n");
log_header(design, "Executing SYNTH_ECP5 pass.\n");
log_push();
@@ -203,7 +203,7 @@ struct SynthEcp5Pass : public ScriptPass
{
if (check_label("begin"))
{
- run("read_verilog -lib +/ecp5/cells_sim.v");
+ run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
@@ -222,11 +222,8 @@ struct SynthEcp5Pass : public ScriptPass
if (!nobram && check_label("bram", "(skip if -nobram)"))
{
- //TODO
-#if 0
- run("memory_bram -rules +/ecp5/brams.txt");
+ run("memory_bram -rules +/ecp5/bram.txt");
run("techmap -map +/ecp5/brams_map.v");
-#endif
}
if (!nodram && check_label("dram", "(skip if -nodram)"))
@@ -258,10 +255,7 @@ struct SynthEcp5Pass : public ScriptPass
run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
- // TODO
-#if 0
run("ecp5_ffinit");
-#endif
}
if (check_label("map_luts"))
@@ -269,14 +263,11 @@ struct SynthEcp5Pass : public ScriptPass
if (abc2 || help_mode) {
run("abc", " (only if -abc2)");
}
- //TODO
-#if 0
run("techmap -map +/ecp5/latches_map.v");
-#endif
if (nomux)
- run("abc -lut 4");
+ run("abc -lut 4 -dress");
else
- run("abc -lut 4:7");
+ run("abc -lut 4:7 -dress");
run("clean");
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-01 13:00:03 +0000