3 files changed, 49 insertions, 0 deletions
diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
new file mode 100644
index 00000000..5554ae31
--- /dev/null
+++ b/techlibs/ice40/tests/.gitignore
@@ -0,0 +1 @@
+test_ffs_[01][01][01][01]_*
diff --git a/techlibs/ice40/tests/test_ffs.sh b/techlibs/ice40/tests/test_ffs.sh
new file mode 100644
index 00000000..5affcbdd
--- /dev/null
+++ b/techlibs/ice40/tests/test_ffs.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+set -ex
+for CLKPOL in 0 1; do
+for ENABLE_EN in 0 1; do
+for RESET_EN in 0 1; do
+for RESET_VAL in 0 1; do
+	pf="test_ffs_${CLKPOL}${ENABLE_EN}${RESET_EN}${RESET_VAL}"
+	sed -e "s/CLKPOL = 0/CLKPOL = ${CLKPOL}/;" -e "s/ENABLE_EN = 0/ENABLE_EN = ${ENABLE_EN}/;" \
+	    -e "s/RESET_EN = 0/RESET_EN = ${RESET_EN}/;" -e "s/RESET_VAL = 0/RESET_VAL = ${RESET_VAL}/;" \
+	    test_ffs.v > ${pf}_gold.v
+	../../../yosys -o ${pf}_gate.v -p "synth_ice40" ${pf}_gold.v
+	../../../yosys -p "proc; opt; test_autotb ${pf}_tb.v" ${pf}_gold.v
+	iverilog -s testbench -o ${pf}_gold ${pf}_gold.v ${pf}_tb.v
+	iverilog -s testbench -o ${pf}_gate ${pf}_gate.v ${pf}_tb.v ../cells_sim.v
+	./${pf}_gold > ${pf}_gold.txt
+	./${pf}_gate > ${pf}_gate.txt
+	cmp ${pf}_gold.txt ${pf}_gate.txt
+done; done; done; done
+echo OK.
diff --git a/techlibs/ice40/tests/test_ffs.v b/techlibs/ice40/tests/test_ffs.v
new file mode 100644
index 00000000..3bef59fb
--- /dev/null
+++ b/techlibs/ice40/tests/test_ffs.v
@@ -0,0 +1,29 @@
+module test(D, C, E, R, Q);
+	parameter [0:0] CLKPOL = 0;
+	parameter [0:0] ENABLE_EN = 0;
+	parameter [0:0] RESET_EN = 0;
+	parameter [0:0] RESET_VAL = 0;
+
+	(* gentb_clock *)
+	input D, C, E, R;
+
+	output Q;
+
+	wire gated_reset = R & RESET_EN;
+	wire gated_enable = E | ~ENABLE_EN;
+	reg posedge_q, negedge_q;
+
+	always @(posedge C, posedge gated_reset)
+		if (gated_reset)
+			posedge_q <= RESET_VAL;
+		else if (gated_enable)
+			posedge_q <= D;
+
+	always @(negedge C, posedge gated_reset)
+		if (gated_reset)
+			negedge_q <= RESET_VAL;
+		else if (gated_enable)
+			negedge_q <= D;
+
+	assign Q = CLKPOL ? posedge_q : negedge_q;
+endmodule