1 files changed, 11 insertions, 0 deletions
diff --git a/tests/asicworld/code_verilog_tutorial_always_example.v b/tests/asicworld/code_verilog_tutorial_always_example.v
new file mode 100644
index 00000000..8b0fc206
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_always_example.v
@@ -0,0 +1,11 @@
+module always_example();
+reg clk,reset,enable,q_in,data;
+
+always @ (posedge clk)
+if (reset)  begin
+   data <= 0;
+end else if (enable) begin   
+   data <= q_in;
+end
+
+endmodule