6 files changed, 24 insertions, 70 deletions
diff --git a/tests/asicworld/code_hdl_models_misc1.v b/tests/asicworld/code_hdl_models_misc1.v
deleted file mode 100644
index e3d9d5d6..00000000
--- a/tests/asicworld/code_hdl_models_misc1.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module misc1 (a,b,c,d,y);
-input a, b,c,d;
-output y;
-
-wire net1,net2,net3;
-
-supply1 vdd;
-supply0 vss;
-
-// y = !((a+b+c).d)
-
-pmos p1 (vdd,net1,a);
-pmos p2 (net1,net2,b);
-pmos p3 (net2,y,c);
-pmos p4 (vdd,y,d);
-
-nmos n1 (vss,net3,a);
-nmos n2 (vss,net3,b);
-nmos n3 (vss,net3,c);
-nmos n4 (net3,y,d);
-
-endmodule
diff --git a/tests/asicworld/code_hdl_models_mux21_switch.v b/tests/asicworld/code_hdl_models_mux21_switch.v
deleted file mode 100644
index 519c07fc..00000000
--- a/tests/asicworld/code_hdl_models_mux21_switch.v
+++ /dev/null
@@ -1,22 +0,0 @@
-//-----------------------------------------------------
-// Design Name : mux21_switch
-// File Name   : mux21_switch.v
-// Function    : 2:1 Mux using Switch Primitives
-// Coder       : Deepak Kumar Tala
-//-----------------------------------------------------
-module mux21_switch (out, ctrl, in1, in2);
-   
-   output out;                    
-   input  ctrl, in1, in2;         
-   wire          w;            
-
-   supply1 power;             
-   supply0 ground;      
-   
-   pmos N1 (w, power, ctrl);     
-   nmos N2 (w, ground, ctrl);   
-   
-   cmos C1 (out, in1, w, ctrl);   
-   cmos C2 (out, in2, ctrl, w);
-   
-endmodule
diff --git a/tests/asicworld/code_hdl_models_nand_switch.v b/tests/asicworld/code_hdl_models_nand_switch.v
deleted file mode 100644
index 1ccdd3a7..00000000
--- a/tests/asicworld/code_hdl_models_nand_switch.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module nand_switch(a,b,out);
-input a,b;
-output out;
-
-supply0 vss;
-supply1 vdd;
-wire net1;
-
-pmos p1 (vdd,out,a);
-pmos p2 (vdd,out,b);
-nmos n1 (vss,net1,a);
-nmos n2 (net1,out,b);
-
-endmodule
-\ No newline at end of file
diff --git a/tests/asicworld/code_hdl_models_t_gate_switch.v b/tests/asicworld/code_hdl_models_t_gate_switch.v
deleted file mode 100644
index 5a7e0eaf..00000000
--- a/tests/asicworld/code_hdl_models_t_gate_switch.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module t_gate_switch (L,R,nC,C);
- inout L;
- inout R;
- input nC;
- input C;
-
- //Syntax: keyword unique_name (drain. source, gate);
- pmos p1 (L,R,nC);
- nmos p2 (L,R,C);
-
-endmodule
diff --git a/tests/asicworld/run-test.sh b/tests/asicworld/run-test.sh
index d5708c45..c22ab692 100755
--- a/tests/asicworld/run-test.sh
+++ b/tests/asicworld/run-test.sh
@@ -11,4 +11,4 @@ do
 done
 shift "$((OPTIND-1))"
 
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS="-e" *.v
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS+="-e" *.v
diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl
new file mode 100644
index 00000000..08bf4ccd
--- /dev/null
+++ b/tests/asicworld/xfirrtl
@@ -0,0 +1,23 @@
+# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
+code_hdl_models_arbiter.v	error: reg rst; cannot be driven by primitives or continuous assignment.
+code_hdl_models_clk_div_45.v	yosys issue: 2nd PMUXTREE pass yields: ERROR: Negative edge clock on FF clk_div_45.$procdff$49.
+code_hdl_models_d_ff_gates.v	combinational loop
+code_hdl_models_d_latch_gates.v	combinational loop
+code_hdl_models_dff_async_reset.v	$adff
+code_hdl_models_tff_async_reset.v	$adff
+code_hdl_models_uart.v	$adff
+code_tidbits_asyn_reset.v	$adff
+code_tidbits_reg_seq_example.v	$adff
+code_verilog_tutorial_always_example.v	empty module
+code_verilog_tutorial_escape_id.v	make_id issues (name begins with a digit)
+code_verilog_tutorial_explicit.v	firrtl backend bug (empty module)
+code_verilog_tutorial_first_counter.v	error: reg rst; cannot be driven by primitives or continuous assignment.
+code_verilog_tutorial_fsm_full.v	error: reg reset; cannot be driven by primitives or continuous assignment.
+code_verilog_tutorial_if_else.v	empty module (everything is under 'always @ (posedge clk)')
+[code_verilog_tutorial_n_out_primitive.v	empty module
+code_verilog_tutorial_parallel_if.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_simple_function.v	empty module (no hardware)
+code_verilog_tutorial_simple_if.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_task_global.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_v2k_reg.v		empty module
+code_verilog_tutorial_which_clock.v	 $adff