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-rw-r--r--tests/techmap/mem_simple_4x1_cells.v13
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/techmap/mem_simple_4x1_cells.v b/tests/techmap/mem_simple_4x1_cells.v
new file mode 100644
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--- /dev/null
+++ b/tests/techmap/mem_simple_4x1_cells.v
@@ -0,0 +1,13 @@
+module MEM4X1 (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);
+ input CLK, WR_DATA, WR_EN;
+ input [3:0] RD_ADDR, WR_ADDR;
+ output reg RD_DATA;
+
+ reg [15:0] memory;
+
+ always @(posedge CLK) begin
+ if (WR_EN)
+ memory[WR_ADDR] <= WR_DATA;
+ RD_DATA <= memory[RD_ADDR];
+ end
+endmodule