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* Added write_smt2 -memClifford Wolf2015-06-14
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* Makefile fix for YosysJS buildClifford Wolf2015-06-11
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* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-11
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* Improvements in cellaigs.cc and "json -aig"Clifford Wolf2015-06-11
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* AigMaker refactoringClifford Wolf2015-06-10
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* Added "json -aig"Clifford Wolf2015-06-10
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* Renamed "aig" to "aigmap"Clifford Wolf2015-06-10
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* Fixed cellaigs port extendingClifford Wolf2015-06-10
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* Added "aig" passClifford Wolf2015-06-09
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* synth_ice40 now flattens by defaultClifford Wolf2015-06-09
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* Added cellaigs APIClifford Wolf2015-06-09
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* Merge clock inverters in memory_dffClifford Wolf2015-06-09
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* Merge branch 'verilog-backend-memV2' of github.com:wluker/yosysClifford Wolf2015-06-09
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| * $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-08
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| * Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-04
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* | Fixed "avail_parameters" handling in module clone/copyClifford Wolf2015-06-08
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* | Added log_dump() support for IdStringsClifford Wolf2015-06-08
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* | Fixed handling of parameters with reversed rangeClifford Wolf2015-06-08
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* Added opt_share -share_allClifford Wolf2015-05-31
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* Added iCE40 PLL cellsClifford Wolf2015-05-31
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* Added liberty dont_use support to dfflibmapClifford Wolf2015-05-31
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* Fixed signedness of genvar expressionsClifford Wolf2015-05-29
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* Added output args to synth_ice40Clifford Wolf2015-05-26
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* Improvements in BLIF front-endClifford Wolf2015-05-24
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* improved ice40 SB_IO sim modelClifford Wolf2015-05-23
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* Improved "flatten" handlings of inout portsClifford Wolf2015-05-23
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* Added simple $dlatch support to opt_rmdffClifford Wolf2015-05-23
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* Added ice40 SB_IO sim modelClifford Wolf2015-05-23
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-05-22
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| * Some fixes for $mem in verilog back-endClifford Wolf2015-05-20
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* | preserve used $-wires with init attribute in opt_cleanClifford Wolf2015-05-22
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* bugfix in blif front-endClifford Wolf2015-05-18
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* added vloghtb test_febe.shClifford Wolf2015-05-17
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* Improved .latch support in BLIF front-endClifford Wolf2015-05-17
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* Added read_blif commandClifford Wolf2015-05-17
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* Generalized blifparse APIClifford Wolf2015-05-17
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* abc/blifparse files reorganizationClifford Wolf2015-05-17
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* Verific build fixesClifford Wolf2015-05-17
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* Added .barbuf support to abc BLIF parserClifford Wolf2015-05-13
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* changed file() to open() in python scriptsClifford Wolf2015-05-11
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* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-11
|\ | | | | Fixed bug in $mem cell verilog code generation.
| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-11
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* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-10
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* Merge pull request #62 from wluker/verilog-backend-memClifford Wolf2015-05-10
|\ | | | | Added support for $mem cells in the verilog backend.
| * Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-10
| | | | | | | | | | | | Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector.
| * Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-08
| | | | | | | | write-enable bits and RD_TRANSPARENT parameter settings.
| * Added support for $mem cells in the verilog backend.luke whittlesey2015-05-07
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* Fixed memory_unpack for initialized memoriesClifford Wolf2015-04-29
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* Preserve important attributes in splitnetsClifford Wolf2015-04-29
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* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-29
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