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Age
*
Added smtbmc.py
Clifford Wolf
2015-10-13
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Added write_smt2 -wires
Clifford Wolf
2015-10-13
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Added examples/ top-level directory
Clifford Wolf
2015-10-13
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SystemVerilog also has assume(), added implicit -D FORMAL
Clifford Wolf
2015-10-13
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Merge branch 'master' of https://github.com/rubund/yosys
Clifford Wolf
2015-10-13
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Use DESTDIR as defined in https://www.gnu.org/prep/standards/html_node/DESTDI...
Ruben Undheim
2015-10-11
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Use LDFLAGS, CXXFLAGS and CPPFLAGS from the environment when building
Ruben Undheim
2015-10-11
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Fixed "flatten" for unconnected inout ports
Clifford Wolf
2015-10-13
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Added support for "parameter" and "localparam" in global context
Clifford Wolf
2015-10-07
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Fixed complexity of assigning to vectors in constant functions
Clifford Wolf
2015-10-01
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Fixed detection of unconditional $readmem[hb]
Clifford Wolf
2015-09-30
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Added edgetypes command
Clifford Wolf
2015-09-27
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Some cleanups in qwp
Clifford Wolf
2015-09-26
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Added "test_cell -noeval"
Clifford Wolf
2015-09-25
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Added wreduce $mul support and fixed signed $mul opt_const bug
Clifford Wolf
2015-09-25
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Bugfix in bram read-enable code
Clifford Wolf
2015-09-25
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Bugfixes in $readmem[hb]
Clifford Wolf
2015-09-25
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Bugfixes in writing of memories as Verilog
Clifford Wolf
2015-09-25
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Fixed segfault in AstNode::asReal
Clifford Wolf
2015-09-25
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Added read-enable to memory model
Clifford Wolf
2015-09-25
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Added pivoting to qwp solver
Clifford Wolf
2015-09-24
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Improved qwp performance
Clifford Wolf
2015-09-24
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Added statistics summary to "qwp"
Clifford Wolf
2015-09-24
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Fixed memory_bram for ROMs in BRAMs with write-enable inputs
Clifford Wolf
2015-09-24
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Fixed AstNode::mkconst_bits() segfault on zero-sized constant
Clifford Wolf
2015-09-24
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Added read_verilog -nodpi
Clifford Wolf
2015-09-23
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Bugfix in handling of multi-dimensional memories
Clifford Wolf
2015-09-23
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Warning for $display/$write outside initial block
Clifford Wolf
2015-09-23
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Fixed support for $write system task
Clifford Wolf
2015-09-23
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Fixed detection of "task foo(bar);" syntax error
Clifford Wolf
2015-09-22
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Fixed multi-level prefix resolving
Clifford Wolf
2015-09-22
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Fixed segfault on invalid verilog constant 1'b_
Clifford Wolf
2015-09-22
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Fixed emcc build
Clifford Wolf
2015-09-21
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Do not detect fsm state registers with init attribute
Clifford Wolf
2015-09-21
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Bugfix in "qwp" pass
Clifford Wolf
2015-09-21
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Improvements and fixes in "qwp" pass
Clifford Wolf
2015-09-21
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Added "qwp -dump"
Clifford Wolf
2015-09-20
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Added "qwp" command
Clifford Wolf
2015-09-20
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Improvements to $display system task
Andrew Zonenberg
2015-09-19
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Added nlutmap
Clifford Wolf
2015-09-18
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Added lut2mux pass
Clifford Wolf
2015-09-18
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Cosmetic fix in Module::addLut()
Clifford Wolf
2015-09-18
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Added buffer detection to "abc -lut"
Clifford Wolf
2015-09-18
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Renamed GreenPAK4 cells, improved GP4 DFF mapping
Clifford Wolf
2015-09-18
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Added support for "dfflibmap -liberty +/..."
Clifford Wolf
2015-09-18
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Added detection of "mux inverter" chains in opt_const
Clifford Wolf
2015-09-18
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Added $logic_not handling to fsm_detect
Clifford Wolf
2015-09-18
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Added $finish and $display to README
Clifford Wolf
2015-09-18
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Merge branch 'feat-finish-disp'
Clifford Wolf
2015-09-18
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Added AST_INITIAL checks for $finish and $display
Clifford Wolf
2015-09-18
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