summaryrefslogtreecommitdiff
Commit message (Expand)AuthorAge
* Fixed oom bug in ilang parserClifford Wolf2015-11-29
* Fixed performance bug in ilang parserClifford Wolf2015-11-27
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-11-26
|\
| * Added PRIM_DLATCHRS support to verific front-endClifford Wolf2015-11-24
* | Removed dangling ';' in rtlil.hClifford Wolf2015-11-26
* | Added ice40_ffinit passClifford Wolf2015-11-26
|/
* Fixed WE/RE usage in iCE40 BRAM mappingClifford Wolf2015-11-24
* Fixed handling of re-declarations of wires in tasks and functionsClifford Wolf2015-11-23
* Added torder commandClifford Wolf2015-11-19
* Fixed performance bug in Verific importerClifford Wolf2015-11-16
* Changes for Verific 3.16_484_32_151112Clifford Wolf2015-11-12
* Link to vlsitechnology.org for liberty filesClifford Wolf2015-11-12
* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-12
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-11
* Added "abc -g"Clifford Wolf2015-11-10
* Merge pull request #97 from zeldin/masterClifford Wolf2015-11-08
|\
| * Fix a segfault in dffinit when the value has too few bitsMarcus Comstedt2015-11-08
|/
* Added "singleton" passClifford Wolf2015-11-07
* Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-06
* Bugfix in mapping $tribuf to $_TBUF_Clifford Wolf2015-11-05
* Bugfix in memory_dffClifford Wolf2015-10-31
* Improvements in wreduceClifford Wolf2015-10-31
* Bugfix in Xilinx LUT mappingClifford Wolf2015-10-30
* Improved SigMap performanceClifford Wolf2015-10-28
* Improvements in new SigMapClifford Wolf2015-10-28
* Use mfp<> in equiv_markClifford Wolf2015-10-27
* Removed old SigMap implementationClifford Wolf2015-10-27
* Added hashlib::mfp and new SigMapClifford Wolf2015-10-27
* Improvements in equiv_structClifford Wolf2015-10-25
* Major refactoring of equiv_structClifford Wolf2015-10-25
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
* Added "equiv_add -cell"Clifford Wolf2015-10-25
* equiv_struct now creates equiv_merged attributesClifford Wolf2015-10-25
* Improvements in equiv_structClifford Wolf2015-10-24
* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-24
* improvement in "stat"Clifford Wolf2015-10-24
* Fixed driver conflict handling (various cmds)Clifford Wolf2015-10-24
* equiv_purge bugfix, using SigChunk in Yosys namespaceClifford Wolf2015-10-24
* Fixed handling of driver-driver conflicts in wreduceClifford Wolf2015-10-24
* Added equiv_mark commandClifford Wolf2015-10-23
* Disabled "Skipping blackbox module" msg in show commandClifford Wolf2015-10-23
* Added support for ":" as comment symbol after ;-parsingClifford Wolf2015-10-23
* Also merge $equiv cells in equiv_structClifford Wolf2015-10-23
* Improvements in equiv_structClifford Wolf2015-10-23
* Added equiv_purgeClifford Wolf2015-10-22
* Added equiv_struct commandClifford Wolf2015-10-21
* Improved inout handling in equiv_makeClifford Wolf2015-10-21
* Progress on cell help messagesClifford Wolf2015-10-20
* Progress on cell help messagesClifford Wolf2015-10-17
* Progress in yosys-smtbmcClifford Wolf2015-10-15