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| * Fixed "make clean" for out-of-tree buildsClifford Wolf2015-08-12
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| * Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
| | | | | | | | This is based on work done by Larry Doolittle
| * Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-12
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| * Fixed hashlib for 64 bit int keysClifford Wolf2015-08-12
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| * Added SMV back-end 'test_cells.sh' scriptClifford Wolf2015-08-12
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* | More ASCII encoding fixesClifford Wolf2015-08-13
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* | Fixed CRLF line endingsClifford Wolf2015-08-13
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* | Some ASCII encoding fixes (comments and docs) by Larry DoolittleClifford Wolf2015-08-13
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* Merge pull request #70 from gaomy3832/bugfixClifford Wolf2015-08-12
|\ | | | | Remove unused blackbox modules in opt_clean.
| * Remove unused blackbox modules in opt_clean.Mingyu Gao2015-08-11
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| * Bugfix for cell hash cache option in opt_share.Mingyu Gao2015-08-10
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* | Bugfix for cell hash cache option in opt_share.Mingyu Gao2015-08-11
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* | Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-11
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* | Added missing ct_all setup to opt_cleanClifford Wolf2015-08-11
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* Use MEMID as name for $mem cellClifford Wolf2015-08-09
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* Merge pull request #69 from zeldin/masterClifford Wolf2015-08-07
|\ | | | | Added iCE40 WARMBOOT cell
| * Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-06
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* Remove some very strange whitespace in btor.cc (by Larry Doolittle)Clifford Wolf2015-08-05
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* Bugfix in SMV back-end for partially unassigned wiresClifford Wolf2015-08-05
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* Added ENABLE_LIBYOSYS Makefile optionClifford Wolf2015-08-04
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* Added $assert support to SMV back-endClifford Wolf2015-08-04
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* Added libyosys.so buildClifford Wolf2015-08-04
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* Merge pull request #68 from zeldin/masterClifford Wolf2015-08-01
|\ | | | | Add -noautowire option to verilog frontend
| * Add -noautowire option to verilog frontendMarcus Comstedt2015-08-01
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* Added WORDS parameter to $meminitClifford Wolf2015-07-31
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* Fixed flatten $meminit handlingClifford Wolf2015-07-30
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* Improvements in BLIF back-endClifford Wolf2015-07-29
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* Fixed nested mem2regClifford Wolf2015-07-29
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* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-27
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* Fixed "check" command for inout portsClifford Wolf2015-07-27
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* Some cleanups in opt_rmdffClifford Wolf2015-07-25
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* Added "miter -assert"Clifford Wolf2015-07-25
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* Keep modules with $assume (like $assert)Clifford Wolf2015-07-25
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* Improved $adff simplificationClifford Wolf2015-07-24
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* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-20
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* Fixed techmap processes error msgClifford Wolf2015-07-18
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* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-18
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* Some fixes in "select" commandClifford Wolf2015-07-16
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* Fixed YosysJS.create_worker() usage of this.url_prefixClifford Wolf2015-07-10
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* Improved liberty file test caseClifford Wolf2015-07-06
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* Updated ABCClifford Wolf2015-07-06
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* Do not collect disabled $memwr cellsClifford Wolf2015-07-06
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* Improved YosysJS WebWorker APIClifford Wolf2015-07-04
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* Bugfix in fsm_extractClifford Wolf2015-07-03
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* Added "synth -nofsm"Clifford Wolf2015-07-02
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* Fixed trailing whitespacesClifford Wolf2015-07-02
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* Added opt_const -clkinvClifford Wolf2015-07-01
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* Added logic-loop error handling to freduceClifford Wolf2015-06-30
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-06-30
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| * Added YosysJS.create_worker()Clifford Wolf2015-06-28
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