Commit message (Expand)AuthorAge
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Improved way of connecting ports in techmap passClifford Wolf2013-10-17
* Only prefer connected signals iff they have public namesClifford Wolf2013-10-17
* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-17
* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-17
* Avoid re-arranging signals on register outputsClifford Wolf2013-10-17
* Fixed detection of major wires in opt_cleanClifford Wolf2013-10-17
* Added iopadmap passClifford Wolf2013-10-16
* Moved dfflibmap from passes/dfflibmap to passes/techmapClifford Wolf2013-10-16
* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-16
* Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'Clifford Wolf2013-10-16
* Added recommended apt-get commands to READMEClifford Wolf2013-10-11
* Fixed minisat includeClifford Wolf2013-10-11
* Pinned ABC revision to 0f9e5488ced3Clifford Wolf2013-10-03
* Improvements in EDIF backendClifford Wolf2013-09-17
* Added additional options to BLIF backendClifford Wolf2013-09-15
* Added BLIF backendClifford Wolf2013-09-15
* A couple of small fixes in SPICE backendClifford Wolf2013-09-15
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Updated manualClifford Wolf2013-09-15
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
* Added spice backendClifford Wolf2013-09-14
* Merge branch 'master' of Wolf2013-09-03
| * Encode large (>32 bits) parameters as hex string in edif backendClifford Wolf2013-08-28
| * Improved edif backendClifford Wolf2013-08-27
| * Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-27
* | Added -selected option to various backendsClifford Wolf2013-09-03
* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-22
* More explicit integer output in verilog backendClifford Wolf2013-08-22
* Added correct encoding of identifiers in EDIF backendClifford Wolf2013-08-22
* Added edif backend (still under construction)Clifford Wolf2013-08-22
* Merge pull request #10 from hansiglaser/masterClifford Wolf2013-08-21
| * fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-21
* | Some minor documentation fixesClifford Wolf2013-08-21
* | Merge pull request #9 from hansiglaser/masterClifford Wolf2013-08-20
| * Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-20
* | Merge pull request #8 from hansiglaser/masterClifford Wolf2013-08-20
| * Added support for notif0/notif1 primitivesJohann Glaser2013-08-20
* Added cleaning of old version_* files to version_* make ruleClifford Wolf2013-08-20
* Added version info to yosys command and added -V optionClifford Wolf2013-08-20
* Minor fixes in abc build instructions and abc passClifford Wolf2013-08-20
* Fixed width and sign detection for ** operatorClifford Wolf2013-08-19
* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-19
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-15
* Fixed signed div/mod in const eval (rounding and stuff)Clifford Wolf2013-08-15
* Added ezsat api for creation of anonymous vectorsClifford Wolf2013-08-15
* Added sat -ignore_div_by_zero switchClifford Wolf2013-08-15
* Added eval -brute_force_equiv_checker_x modeClifford Wolf2013-08-15
* Added support for "2**n" shifter encodingClifford Wolf2013-08-12