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Age
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Added a warning note about error reporting to read_verilog help message
Clifford Wolf
2014-02-16
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Progress in presentation
Clifford Wolf
2014-02-16
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Fixed use of selection in splitnets command
Clifford Wolf
2014-02-16
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Added recursion support to techmap
Clifford Wolf
2014-02-16
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Progress in presentation
Clifford Wolf
2014-02-16
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Progress in presentation
Clifford Wolf
2014-02-16
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Improved support for constant functions
Clifford Wolf
2014-02-16
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Now we are in Yoys 0.2.0+ development
Clifford Wolf
2014-02-16
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Tagging Yoys 0.2.0
Clifford Wolf
2014-02-16
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Added != support for relational select pattern
Clifford Wolf
2014-02-16
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Added iopadmap -bits
Clifford Wolf
2014-02-15
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Added ff and latch support to read_liberty
Clifford Wolf
2014-02-15
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Bugfix in expression parser of read_liberty
Clifford Wolf
2014-02-15
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Fixed dfflibmap for cell libraries with no set-reset-ff
Clifford Wolf
2014-02-15
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Correctly convert constants to RTLIL (fixed undef handling)
Clifford Wolf
2014-02-15
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Added frontend (-f) option to autotest.sh
Clifford Wolf
2014-02-15
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Fixed opt_const handling of double invert with non-1 output width
Clifford Wolf
2014-02-15
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Added liberty frontend
Clifford Wolf
2014-02-15
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Be more conservative with new const-function code
Clifford Wolf
2014-02-14
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Added support for FOR loops in function calls in parameters
Clifford Wolf
2014-02-14
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Created basic support for function calls in parameter values
Clifford Wolf
2014-02-14
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Added abc -keepff option
Clifford Wolf
2014-02-14
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updated default ABC command strings
Clifford Wolf
2014-02-13
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Updated ABC
Clifford Wolf
2014-02-13
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Implemented read_verilog -defer
Clifford Wolf
2014-02-13
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Removed double blanks in ABC default command sequences
Clifford Wolf
2014-02-13
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2014-02-13
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Merge pull request #26 from ahmedirfan1983/btor
Clifford Wolf
2014-02-12
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modified btor synthesis script for correct use of splice command.
Ahmed Irfan
2014-02-12
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disabling splice command in the script
Ahmed Irfan
2014-02-11
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register output corrected
Ahmed Irfan
2014-02-11
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Ahmed Irfan
2014-02-11
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added concat and slice cell translation
Ahmed Irfan
2014-02-11
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Updated ABC and some related changes
Clifford Wolf
2014-02-13
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2014-02-12
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Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)
Clifford Wolf
2014-02-12
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Added support for functions returning integer
Clifford Wolf
2014-02-12
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Updated ABC to rev e97a6e1d59b9
Clifford Wolf
2014-02-12
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renamed ilang "scope error" to "ilang error"
Clifford Wolf
2014-02-11
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More Makefile cleanups
Clifford Wolf
2014-02-11
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Improved "make manual" and "make clean"
Clifford Wolf
2014-02-11
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Improved ilang parser error messages
Clifford Wolf
2014-02-09
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fixed a bug in subcircuit library with cells that have connections to itself
Clifford Wolf
2014-02-09
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Various improvements in expose command (added -sep and -cut)
Clifford Wolf
2014-02-09
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Added delete {-input|-output|-port}
Clifford Wolf
2014-02-09
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Bugfix in delete command
Clifford Wolf
2014-02-09
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Added test cases for expose -evert-dff
Clifford Wolf
2014-02-08
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Fixed handling of async reset in expose -evert-dff
Clifford Wolf
2014-02-08
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Build fixes for log cmd
Clifford Wolf
2014-02-08
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2014-02-08
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