yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed comments in manual rtlil/ilang syntax	Clifford Wolf	2013-07-25
*	Added RTLIL and Liberty syntax highlighting to manual	Clifford Wolf	2013-07-25
*	Automatically run "proc" on extract map files	Clifford Wolf	2013-07-24
*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23
*	Fixed "make clean" for manual files	Clifford Wolf	2013-07-23
*	Added web site link to README	Clifford Wolf	2013-07-21
*	Added Yosys Manual	Clifford Wolf	2013-07-20
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12
*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12
*	Added ast frontend refactoring to TODO	Clifford Wolf	2013-07-11
*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11
*	Bugfixes for empty signal vectors	Clifford Wolf	2013-07-10
*	Fixed sign propagation in bit-wise operators	Clifford Wolf	2013-07-09
*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09
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\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07
*	Removed tests/xsthammer	Clifford Wolf	2013-07-07
*	Added opt_clean -purge option	Clifford Wolf	2013-07-07
*	Fixed handling of $eq and $ne in opt_const	Clifford Wolf	2013-07-07
*	Fixed vivado related xsthammer bugs	Clifford Wolf	2013-07-05
*	Various improvements in xsthammer report generator	Clifford Wolf	2013-07-05
*	Added work-around to isim bug in xsthammer report script	Clifford Wolf	2013-07-05
*	Fixed gcc warnings in ezminisat	Clifford Wolf	2013-07-05
*	Added CARRY4 Xilinx cell to xsthammer cell lib	Clifford Wolf	2013-07-05
*	Added xsthammer report generator	Clifford Wolf	2013-07-05
*	Improved xsthammer quartus support	Clifford Wolf	2013-07-04
*	Added Altera Cyclon III cell library to xsthammer	Clifford Wolf	2013-07-04
*	Documentation updates	Clifford Wolf	2013-07-04
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
*	Added QMAKE makefile variable	Clifford Wolf	2013-07-03
*	Added Altera Quartus support to xsthammer	Clifford Wolf	2013-07-03
*	Progress in xsthammer	Clifford Wolf	2013-07-03
*	Added vivado support to xsthammer	Clifford Wolf	2013-06-26
*	Added SAT support for -all/-max with -verify	Clifford Wolf	2013-06-23
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-06-20
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\| *	Added renaming of wires and cells to "rename" command	Clifford Wolf	2013-06-19
* \|	Added timout functionality to SAT solver	Clifford Wolf	2013-06-20
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*	Added "eval" pass	Clifford Wolf	2013-06-19
*	Fixed build with clang	Clifford Wolf	2013-06-18
*	Added splitnets command	Clifford Wolf	2013-06-18
*	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	Clifford Wolf	2013-06-18
*	Added more stuff to xsthammer, found first xst bug	Clifford Wolf	2013-06-17
*	Added support for "assign" statements in abc vlparse	Clifford Wolf	2013-06-15
*	Added ternary op and concat op to xsthammer	Clifford Wolf	2013-06-15
*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14
*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13
*	More xsthammer improvements (using xst 14.5 now)	Clifford Wolf	2013-06-13