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* Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."Clifford Wolf2014-10-30
* Improved nomem2reg documentationClifford Wolf2014-10-30
* Added support for empty lines to here documentsClifford Wolf2014-10-29
* AST simplifier: optimize constant AST_CASE nodes before recursively descendingClifford Wolf2014-10-29
* Added support for task and function args in parenthesesClifford Wolf2014-10-27
* Improvements in $readmem[bh] implementationClifford Wolf2014-10-26
* Added support for $readmemh/$readmembClifford Wolf2014-10-26
* Fixed constant "cond ? string1 : string2" with strings of different sizeClifford Wolf2014-10-25
* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-23
* minor indenting correctionsClifford Wolf2014-10-19
* Merge pull request #40 from parvizp/compile_mac_10.9.2Clifford Wolf2014-10-19
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| * Builds on Mac 10.9.2 with LLVM 3.5.Parviz Palangpour2014-10-19
* | Improved new_id() for win32Clifford Wolf2014-10-18
* | Also look for yosys-abc in parent dir on win32Clifford Wolf2014-10-18
* | Various improvements to version reporting on win32Clifford Wolf2014-10-18
* | Disabled READLINE in MXE cross buildClifford Wolf2014-10-18
* | Fixed typo in test_cellClifford Wolf2014-10-18
* | Fixed shell prompt and proc_self_dirname() for win32Clifford Wolf2014-10-18
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* Fixed various VS warningsClifford Wolf2014-10-18
* Create vcxsrc in mxe build "make dist"Clifford Wolf2014-10-18
* Moved yosys-config.in to misc/Clifford Wolf2014-10-18
* Added notes regarding building in VSClifford Wolf2014-10-17
* Added vcxproj_files.txt to MXE "make dist"Clifford Wolf2014-10-17
* More win32 (mxe and vs) build fixesClifford Wolf2014-10-17
* Various win32 / vs build fixesClifford Wolf2014-10-17
* Added genfiles.zip to MXE "make dist"Clifford Wolf2014-10-17
* Various MXE build fixesClifford Wolf2014-10-17
* Header changes so it will compile on VSWilliam Speirs2014-10-17
* Wrapped math in int constructorWilliam Speirs2014-10-17
* Fixed a few VS warningsClifford Wolf2014-10-17
* Don't be too smart with $dff cells with "init" attribute on out signalClifford Wolf2014-10-16
* Some cleanups in opt_cleanClifford Wolf2014-10-16
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-16
* Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selectsClifford Wolf2014-10-16
* Fixed handling of invalid array access in mem2reg codeClifford Wolf2014-10-16
* Replaced log_assert() do { ... } while (0) hack with a static inline functionClifford Wolf2014-10-15
* Fixed gcc warningClifford Wolf2014-10-15
* Fixed MXE buildClifford Wolf2014-10-15
* Merge branch 'win32'Clifford Wolf2014-10-15
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| * Check for _YOSYS_ in yosys.hClifford Wolf2014-10-15
| * Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-15
| * Replaced readsome() with read() and gcount()Clifford Wolf2014-10-15
| * A few indent fixesClifford Wolf2014-10-15
| * Changed from "and" to "&&"William Speirs2014-10-15
| * Changed to explicit heap allocated memoryWilliam Speirs2014-10-15
| * Wrapped init in std::set constructorWilliam Speirs2014-10-15
| * Made iterators extend std::iterator and added == operatorWilliam Speirs2014-10-15
| * Define empty __attribute__ macro for non-gcc, non-clang compilersClifford Wolf2014-10-15
| * Fixed log so it will compile under Visual StudioWilliam Speirs2014-10-15
| * Updated lexers & parsers to include prefixesWilliam Speirs2014-10-15
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